SLASF62A June 2024 – November 2024 DAC80516
PRODUCTION DATA
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When writing to the device, the value for the address register is the first byte transferred after the target address byte with the R/W bit low. Every write operation to the device requires a value for the address register, as shown in Figure 6-2.
When reading from the device, the last value stored in the address register by a write operation is used to determine which register is read by a read operation. To change which register is read for a read operation, a new value must be written to the address register. This transaction is accomplished by issuing a target address byte with the R/W bit low, followed by the address register byte; no additional data are required. The controller can then generate a START condition and send the target address byte with the R/W bit high to initiate the read command.
If repeated reads from the same register are desired, there is no need to continually send the address register bytes because the device retains the address register value until the value is changed by the next write operation. The register bytes are big endian and left justified.
Terminate read operations by issuing a not-acknowledge command at the end of the last byte to be read. The controller must leave the SDA line high during the acknowledge time of the last byte that is read from the target, as shown in Figure 6-3.
Block access functionality is provided to minimize the transfer overhead of large data sets. Block access enables multibyte transfers and is configured by setting the block access bit high. Until the transaction is terminated by the STOP condition, the device reads and writes the subsequent memory locations, as shown in Figure 6-4 and Figure 6-5. If the controller reaches address 0x7F in a page, the device continues reading and writing from this address until the transaction is terminated.