SLASF62A June   2024  – November 2024 DAC80516

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. Register Map
    1. 7.1 DAC80516 Registers
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

I2C Read and Write Operations

When writing to the device, the value for the address register is the first byte transferred after the target address byte with the R/W bit low. Every write operation to the device requires a value for the address register, as shown in Figure 6-2.

DAC80516 I2C Write Access Protocol Figure 6-2 I2C Write Access Protocol

When reading from the device, the last value stored in the address register by a write operation is used to determine which register is read by a read operation. To change which register is read for a read operation, a new value must be written to the address register. This transaction is accomplished by issuing a target address byte with the R/W bit low, followed by the address register byte; no additional data are required. The controller can then generate a START condition and send the target address byte with the R/W bit high to initiate the read command.

If repeated reads from the same register are desired, there is no need to continually send the address register bytes because the device retains the address register value until the value is changed by the next write operation. The register bytes are big endian and left justified.

Terminate read operations by issuing a not-acknowledge command at the end of the last byte to be read. The controller must leave the SDA line high during the acknowledge time of the last byte that is read from the target, as shown in Figure 6-3.

DAC80516 I2C Read Access Protocol Figure 6-3 I2C Read Access Protocol

Block access functionality is provided to minimize the transfer overhead of large data sets. Block access enables multibyte transfers and is configured by setting the block access bit high. Until the transaction is terminated by the STOP condition, the device reads and writes the subsequent memory locations, as shown in Figure 6-4 and Figure 6-5. If the controller reaches address 0x7F in a page, the device continues reading and writing from this address until the transaction is terminated.

DAC80516 I2C Block Write Access Figure 6-4 I2C Block Write Access
DAC80516 I2C Block Read Access Figure 6-5 I2C Block Read Access