The update mode for each DAC channel is determined by the DAC synchronous setting, configured for each DAC by writing to the SYNC_EN register. In asynchronous mode, a write to the DAC buffer data register results in an immediate update of the DAC active registers on a CS rising edge. In synchronous mode, writing to the DAC buffer data register does not automatically update the DAC active register. Instead, the update occurs only after a DAC trigger signal is generated. A DAC trigger signal can be generated by pulling the LDAC pin low, which updates the active registers of all DAC output channels operating in synchronous mode simultaneously. The LDAC pin does not affect the active registers of channels already configured as asynchronous in the SYNC_EN register; however all other channels (configured as synchronous in the SYNC_EN register) operate in asynchronous mode as long as the LDAC pin is held at logic low. A DAC trigger can also be generated through software, by writing to the appropriate LDAC_OUTn bit in the TRIGGER register. A software trigger updates the active registers of two DAC channels at a time; each bit in the TRIGGER register corresponds to a pair of output channels, and setting a bit to 1 updates both corresponding channels simultaneously.