The device is I²C compatible. In I²C protocol, the device that initiates the transfer is called a controller, and a device controlled by the controller is called a target. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated. A START condition is indicated by pulling the data line (SDA) from a high-to-low logic level while SCL is high. All targets on the bus receive the target address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target being addressed responds to the controller by generating an acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted as a control signal.

After all data have been transferred, the controller generates a STOP condition. A STOP condition is indicated by pulling SDA from low to high, while SCL is high.