デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
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16 ビット DAC80516 は、低消費電力、16 チャネル、バッファ付き、電圧出力の D/A コンバータ (DAC) です。DAC80516 には 2.5V、5ppm/℃の内部基準電圧が搭載されているため、ほとんどのアプリケーションで外付けの高精度基準電圧を必要としません。ユーザーが選択可能なゲイン構成を使用して、 2.5V または 5V のフルスケール出力電圧を供給できます。DAC80516 は、単一電源で動作します。
DAC80516 との通信は、SPI および I2C をサポートするシリアル インターフェイスで行われ、最大 50MHz のクロック速度で動作します (デバイスに対する SPI 書き込み中)。VIO ピンにより、 1.7V~5.5V のシリアル インターフェイス動作が可能です。DAC80516 の柔軟なインターフェイスにより、業界標準の広範なマイクロプロセッサやマイクロコントローラとの動作が可能です。
DAC80516 は、-40℃~+125℃の温度範囲で動作が規定されており、小型の WQFN パッケージで供給されます。
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | OUT0 | Output | DAC output channel 0 |
2 | AVDD | Power | Analog power supply |
3 | SCL/CS | Input | I2C: Clock input. SPI: Active-low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, this pin enables the serial interface input shift register. |
4 | SDA/SCLK | Input/Output | I2C: Bidirectional data line SPI: Clock input |
5 | A0/SDI | Input | I2C: Target address selector SPI: Data input. Data are clocked into the input shift register on each falling edge of the SCLK pin. |
6 | FLEXIO | Input/Output | FLEXIO pin, including GPIO and CLEAR pin functionality |
7 | OUT8 | Output | DAC output channel 8 |
8 | OUT9 | Output | DAC output channel 9 |
9 | OUT10 | Output | DAC output channel 10 |
10 | OUT11 | Output | DAC output channel 11 |
11 | OUT12 | Output | DAC output channel 12 |
12 | OUT13 | Output | DAC output channel 13 |
13 | OUT14 | Output | DAC output channel 14 |
14 | OUT15 | Output | DAC output channel 15 |
15 | GND | Power | Ground reference point for all circuitry on the device |
16 | GND | Power | Ground reference point for all circuitry on the device |
17 | LDAC | Input | Active-low DAC synchronization signal. A high-to-low transition on the LDAC pin simultaneously updates the outputs configured in synchronous mode |
18 | VIO | Power | IO supply voltage. This pin sets the I/O operating voltage for the device. |
19 | A1/SDO | Input/Output | I2C: Target address selector. SPI: Data output. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit. |
20 | RESET | Input | Active low reset input, logic low on this pin causes the device to initiate a reset event |
21 | REF | Input/Output | DAC voltage reference input/output. This pin acts as input pin REFIN by default (with internal reference disabled). If internal reference is enabled, this pin acts as output pin REFOUT. |
22 | OUT7 | Output | DAC output channel 7 |
23 | OUT6 | Output | DAC output channel 6 |
24 | OUT5 | Output | DAC output channel 5 |
25 | OUT4 | Output | DAC output channel 4 |
26 | OUT3 | Output | DAC output channel 3 |
27 | OUT2 | Output | DAC output channel 2 |
28 | OUT1 | Output | DAC output channel 1 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
AVDD | Analog supply voltage, AVDD to GND | –0.3 | 6 | V |
VIO | Digital supply voltage, VIO to GND | –0.3 | AVDD | V |
Analog output (OUT) pin voltage | –0.3 | AVDD + 0.3 | V | |
Reference pin voltage | –0.3 | AVDD + 0.3 | V | |
Serial interface pin voltage | –0.3 | VIO + 0.3 | V | |
TJ | Operating junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2500 | V |
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD | Analog supply voltage, AVDD to GND | 2.7 | 5.5 | V | |
VIO | IO supply voltage, VIO to GND | 1.7 | AVDD | V | |
Serial interface input voltage to GND | 0 | VIO | V | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DAC80516 | UNIT | |
---|---|---|---|
RUY (WQFN) | |||
28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 39.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 24.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.9 | °C/W |
ΨJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ΨJB | Junction-to-board characterization parameter | 15.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE (1) | ||||||
Resolution | 16 | Bits | ||||
INL | Relative accuracy | ±1 | ±2 | LSB | ||
DNL | Differential nonlinearity | -1 | ±0.6 | 1 | LSB | |
TUE | Total unadjusted error | DAC output range = 0V to 5V | ±0.04 | ±0.15 | %FSR | |
Offset error | Gain = 1 or 2 | ±0.75 | ±3 | mV | ||
Zero-scale error | DAC register loaded with all zeroes | 0 | 0.5 | 3 | mV | |
Full-scale error | DAC register loaded at full-scale code (65535d), DAC output range = 0V to 5V | ±0.04 | ±0.15 | %FSR | ||
Gain error | Gain = 1 or 2 | ±0.04 | ±0.15 | %FSR | ||
Offset error drift | ±3 | µV/°C | ||||
Zero-scale error drift | ±2 | µV/°C | ||||
Full-scale error drift | ±3 | ppm FSR/°C | ||||
Gain error drift | ±2 | ppm FSR/°C | ||||
Output voltage drift over time | TJ = 25°C, DAC code = midscale, 1900 hours |
20 | ppm FSR | |||
OUTPUT CHARACTERISTICS | ||||||
Output voltage(2) | Gain = 2 | 0 | 2 × VREF | V | ||
Gain = 1 | 0 | VREF | ||||
Output voltage headroom | To AVDD (–50mA ≤ IOUT ≤ 50mA), DAC code = full-scale |
0.5 | V | |||
Load current | 50 | mA | ||||
Short-circuit current(3) | Full-scale output shorted to GND | 75 | mA | |||
Zero-scale output shorted to VDD | 75 | |||||
Capacitive load(4) | RLOAD = open | 0 | 2 | nF | ||
DC output impedance | DAC output at AVDD/2 | 0.08 | Ω | |||
DAC output at AVDD or GND | 10 | |||||
DYNAMIC PERFORMANCE | ||||||
Output voltage settling time | ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, AVDD = 5.5V, VREFIN = 2.5V, gain = 2 |
6 | µs | |||
Slew rate | AVDD = 5.5V, VREFIN = 2.5V | 1.7 | V/µs | |||
Power-on glitch magnitude | DAC code = zero scale | 25 | mV | |||
Output noise | 0.1Hz to 10Hz, DAC code = midscale | 12 | µVpp | |||
Output noise density | 1kHz, DAC code = midscale, AVDD = 5.5V, VREFIN = 2.5V |
65 | nV/Hz | |||
AC PSRR | DAC code = midscale, frequency = 60Hz, amplitude 200mVpp superimposed on AVDD | 80 | dB | |||
DC PSRR | DAC code = midscale, AVDD = 5V ±0.5V | 0.02 | mV/V | |||
Code change glitch impulse | 1LSB change around major carrier | 1 | nV-s | |||
Channel-to-channel ac crosstalk | DAC code = zero scale, full-scale swing on adjacent channel | 1 | nV-s | |||
Channel-to-channel dc crosstalk | Measured channel at zero scale, adjacent channel at full scale |
12 | µV | |||
Measured channel at zero scale, all other channels at full scale |
12 | |||||
Digital feedthrough | DAC code = midscale, fSCLK = 1MHz | 0.1 | nV-s | |||
Power-up time(5) | Time for DAC channels to power on and output 0V after AVDD ramps to 2.4V, VREFIN = 2.5V. | 120 | µs | |||
EXTERNAL REFERENCE INPUT | ||||||
VREFIN | Reference input voltage range | Gain = 1 | 1 | VDD | V | |
Gain = 2 | 1 | AVDD/2 | ||||
Reference input current | VREFIN = 2.5V | 85 | µA | |||
Reference input impedance | 25 | 30 | kΩ | |||
Reference input capacitance | 5 | pF | ||||
INTERNAL REFERENCE | ||||||
VREFOUT | Reference output voltage range | TJ = 25°C | 2.4975 | 2.5025 | V | |
Reference output drift | 5 | 10 | ppm/°C | |||
Reference output impedance | 0.2 | Ω | ||||
Reference output noise | 0.1Hz to 10Hz | 10 | µVpp | |||
Reference output noise density | 10kHz, reference load = 10nF | 125 | nV/Hz | |||
Reference load current | -4 | 10 | mA | |||
Reference load regulation | Source and sink | 175 | µV/mA | |||
Reference line regulation | 500 | µV/V | ||||
DIGITAL INPUTS AND OUTPUTS | ||||||
VIH | High-level input voltage, VIH | AVDD = 2.7V to 5.5V | 0.7 × VIO | V | ||
VIL | Low-level input voltage, VIL | AVDD = 2.7V to 5.5V | 0.3 × VIO | V | ||
Input current | ±2 | µA | ||||
Input pin capacitance | 8 | pF | ||||
VOH | High-level output voltage, VOH | IOH = 0.2mA | VIO - 0.2 | V | ||
VOL | Low-level output voltage, VOL | IOL = 0.2mA | 0.4 | V | ||
Output pin capacitance | 4 | pF | ||||
POWER REQUIREMENTS | ||||||
IAVDD | AVDD supply current | Active mode, internal reference enabled, DAC code = full-scale, SPI static | 8.5 | 13 | mA | |
Active mode, internal reference disabled, DAC code = full-scale, SPI static | 8 | 12.5 | ||||
AVDD supply current | Power-down mode | 10 | 20 | µA | ||
IVIO | VIO supply current | 0.1 | 1 | µA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 100 | kHz | ||
tBUF | Bus free time between stop and start conditions | 4.7 | µs | ||
tHDSTA | Hold time after repeated start | 4 | µs | ||
tSUSTA | Repeated start setup time | 4.7 | µs | ||
tSUSTO | Stop condition setup time | 4 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 250 | ns | ||
tLOW | SCL clock low period | 4700 | ns | ||
tHIGH | SCL clock high period | 4000 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 1000 | ns | ||
tVD_DAT | Data valid time | 3.45 | µs | ||
tVD_ACK | Data valid acknowledge time | 3.45 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 400 | kHz | ||
tBUF | Bus free time between stop and start conditions | 1.3 | µs | ||
tHDSTA | Hold time after repeated start | 0.6 | µs | ||
tSUSTA | Repeated start setup time | 0.6 | µs | ||
tSUSTO | Stop condition setup time | 0.6 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 100 | ns | ||
tLOW | SCL clock low period | 1300 | ns | ||
tHIGH | SCL clock high period | 600 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 300 | ns | ||
tVD_DAT | Data valid time | 0.9 | µs | ||
tVD_ACK | Data valid acknowledge time | 0.9 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 1 | MHz | ||
tBUF | Bus free time between stop and start conditions | 0.5 | µs | ||
tHDSTA | Hold time after repeated start | 0.26 | µs | ||
tSUSTA | Repeated start setup time | 0.26 | µs | ||
tSUSTO | Stop condition setup time | 0.26 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 50 | ns | ||
tLOW | SCL clock low period | 0.5 | µs | ||
tHIGH | SCL clock high period | 0.26 | µs | ||
tF | Clock and data fall time | 120 | ns | ||
tR | Clock and data rise time | 120 | ns | ||
tVD_DAT | Data valid time | 0.45 | µs | ||
tVD_ACK | Data valid acknowledge time | 0.45 | µs |