SLASF62 June   2024 DAC80516

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

6.4.1 Clear Mode

Each DAC can be set to enter a clear state using either hardware or software. When a DAC enters the clear state, the DAC is loaded with the data stored in the corresponding CLEAR_CODE register (code 0 by default) and the output is set to the corresponding voltage level.

The DAC buffer and active registers do not change when the DACs enter the clear state, which enables the DAC to return to the operating point prior to the clear event. The DAC buffer and active registers can also be updated while the DAC is in clear state, thus allowing the DAC to output a new value upon return to normal operation.When the DAC exits the clear state, the DAC is immediately loaded with the data in the active register, and the DAC output channel is set back to the corresponding level to restore operation.

By writing to the appropriate bits in the CLEAR register, each DAC can be programmed to enter or exit the clear state. Each DAC can also be forced to enter a clear state through the FLEXIO pin, when configured as an active-low CLEAR pin. This configuration is done by setting the FLEXIO_FUNC bit in the GEN_CONFIG register (by default, this bit is 0, and FLEXIO acts as a general purpose input-output pin). By default, each DAC output is automatically cleared when the CLEAR pin is asserted to a logic-low level, unless the appropriate bit in the CLEAR_PIN_MASK register is set. After the DAC leaves the clear state, the DAC is reloaded with the contents of the active register and the DAC output channel updates accordingly.

The device also allows user to set a common clear code for each DAC, which can be done by writing to the BCAST_CLR_DATA register. The value stored in this register is written to the CLEAR_CODE registers of all DACs operating in broadcast mode (determined by the appropriate bit setting in the BCAST_EN register), which can be used to clear multiple DACs channels to the same code simultaneously.

If a DAC channel is in a power-down state for any reason, any clear commands are ignored on the DAC until the channel exits the power-down state.