SLASF62A June   2024  – November 2024 DAC80516

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

6.5.2.1 SPI Bus Overview

A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is 24 bits long, thus the CS pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the CS pin is deasserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle contains more than the minimum clock edges, only the last 24 bits are used by the device. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.

In a serial interface access cycle, the first byte input to SDI is the instruction cycle that identifies the request as a read or write command, and the 7-bit address to be accessed. The following bits in the cycle form the data cycle, as shown in Table 6-4.

Table 6-4 SPI Serial Interface Access Cycle
BITFIELDDESCRIPTION
23RWIdentifies the communication as a read or write command to the addressed register.
RW = 0 sets a write operation.
RW = 1 sets a read operation.
22:16A[6:0]Register address. Specifies the register to be accessed during the read or write operation.
15:0DI[15:0]Data cycle bits.
If a write command, the data cycle bits are the values to be written to the register with address A[6:0].
If a read command, the data cycle bits are don’t care values.

Read operations require that the SDO pin is first enabled by setting the SDO_EN bit. A read operation is initiated by issuing a read command access cycle. After the read command, a second access cycle must be issued to get the requested data, formatted as shown in Table 6-5. Data are clocked out on the SDO pin on SCLK rising or falling edges, according to the FSDO bit setting.

Table 6-5 SDO Output Access Cycle
BITFIELDDESCRIPTION
23RWEcho RW bit from previous access cycle.
22:16STATUS[6:0]Lower seven bits of the STATUS register.
15:0DO[15:0]Readback data requested on previous access cycle.