SLASF62A June   2024  – November 2024 DAC80516

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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発注情報

5.5 Electrical Characteristics

at TJ = –40°C to +125°C, AVDD = 2.7V to 5.5V, VIO = 1.7V to AVDD, VREFIN = 2.4V to 5.5V, DAC outputs unloaded, and digital inputs at VIO or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE (1)
Resolution 16 Bits
INL Relative accuracy ±1 ±2 LSB
DNL Differential nonlinearity -1 ±0.6 1 LSB
TUE Total unadjusted error DAC output range = 0V to 5V  ±0.04 ±0.15 %FSR
Offset error Gain = 1 or 2 ±0.75 ±3 mV
Zero-scale error DAC register loaded with all zeroes 0 0.5 3 mV
Full-scale error DAC register loaded at full-scale code (65535d), DAC output range = 0V to 5V ±0.04 ±0.15 %FSR
Gain error Gain = 1 or 2 ±0.04 ±0.15 %FSR
Offset error drift ±3 µV/°C
Zero-scale error drift ±2 µV/°C
Full-scale error drift ±3 ppm FSR/°C
Gain error drift ±2 ppm FSR/°C
Output voltage drift over time TJ = 25°C, DAC code = midscale,
1900 hours		 20 ppm FSR
OUTPUT CHARACTERISTICS
Output voltage(2) Gain = 2  0 2 × VREF V
Gain = 1 0 VREF
Output voltage headroom To AVDD (–50mA ≤ IOUT ≤ 50mA), 
DAC code = full-scale		 0.5 V
Load current 50 mA
Short-circuit current(3) Full-scale output shorted to GND 75 mA
Zero-scale output shorted to VDD 75
Capacitive load(4) RLOAD = open 0 2 nF
DC output impedance DAC output at AVDD/2 0.08 Ω
DAC output at AVDD or GND 10
DYNAMIC PERFORMANCE
Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, AVDD = 5.5V,
VREFIN = 2.5V, gain = 2		 6 µs
Slew rate AVDD = 5.5V, VREFIN = 2.5V 1.7 V/µs
Power-on glitch magnitude DAC code = zero scale 25 mV
Output noise 0.1Hz to 10Hz, DAC code = midscale 12 µVpp
Output noise density 1kHz, DAC code = midscale,
AVDD = 5.5V, VREFIN = 2.5V		 65 nV/Hz
AC PSRR DAC code = midscale, frequency = 60Hz, amplitude 200mVpp superimposed on AVDD 80 dB
DC PSRR DAC code = midscale, AVDD = 5V ±0.5V 0.02 mV/V
Code change glitch impulse 1LSB change around major carrier 1 nV-s
Channel-to-channel ac crosstalk DAC code = zero scale, full-scale swing on adjacent channel 1 nV-s
Channel-to-channel dc crosstalk Measured channel at zero scale,
adjacent channel at full scale		 12 µV
Measured channel at zero scale,
all other channels at full scale		 12
Digital feedthrough DAC code = midscale, fSCLK = 1MHz 0.1 nV-s
Power-up time(5) Time for DAC channels to power on and output 0V after AVDD ramps to 2.4V, VREFIN = 2.5V.  120 µs
EXTERNAL REFERENCE INPUT
VREFIN Reference input voltage range Gain = 1 1 VDD V
Gain = 2 1 AVDD/2
Reference input current VREFIN = 2.5V 85 µA
Reference input impedance 25 30 kΩ
Reference input capacitance 5 pF
INTERNAL REFERENCE
VREFOUT Reference output voltage range TJ = 25°C 2.4975 2.5025 V
Reference output drift 5 10 ppm/°C
Reference output impedance 0.2 Ω
Reference output noise 0.1Hz to 10Hz 10 µVpp
Reference output noise density 10kHz, reference load = 10nF 125 nV/Hz
Reference load current -4 10 mA
Reference load regulation Source and sink 175 µV/mA
Reference line regulation 500 µV/V
DIGITAL INPUTS AND OUTPUTS
VIH High-level input voltage, VIH AVDD = 2.7V to 5.5V 0.7 × VIO V
VIL Low-level input voltage, VIL AVDD = 2.7V to 5.5V 0.3 × VIO V
Input current ±2 µA
Input pin capacitance 8 pF
VOH High-level output voltage, VOH IOH = 0.2mA VIO - 0.2 V
VOL Low-level output voltage, VOL IOL = 0.2mA 0.4 V
Output pin capacitance 4 pF
POWER REQUIREMENTS
IAVDD AVDD supply current Active mode, internal reference enabled, DAC code = full-scale, SPI static 8.5 13 mA
Active mode, internal reference disabled, DAC code = full-scale, SPI static 8 12.5
AVDD supply current Power-down mode 10 20 µA
IVIO VIO supply current 0.1 1 µA
(1) End point fit between codes 256 to 65280
(2) When using an external reference VREF = VREFIN. Otherwise, VREF = 2.5V (internal reference voltage)
(3) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation at temperatures greater than the specified maximum junction temperature can impair device reliability.
(4) Specified by design and characterization, not production tested.
(5) For a further period of time equal to approximately 5ms, SPI or I2C communication to the device is blocked while the device loads internal calibration coefficients from memory.  Any digital communication during this timeframe is ignored.