JAJSUV8 June 2024 DAC80516
ADVANCE INFORMATION
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 400 | kHz | ||
tBUF | Bus free time between stop and start conditions | 1.3 | µs | ||
tHDSTA | Hold time after repeated start | 0.6 | µs | ||
tSUSTA | Repeated start setup time | 0.6 | µs | ||
tSUSTO | Stop condition setup time | 0.6 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 100 | ns | ||
tLOW | SCL clock low period | 1300 | ns | ||
tHIGH | SCL clock high period | 600 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 300 | ns | ||
tVD_DAT | Data valid time | 0.9 | µs | ||
tVD_ACK | Data valid acknowledge time | 0.9 | µs |