SLASF62A June   2024  – November 2024 DAC80516

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 DAC80516 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RUY|28
サーマルパッド・メカニカル・データ
発注情報

5.9 Timing Requirements - SPI

at TJ = –40°C to +125°C, AVDD = 2.7V to 5.5V, VIO = 1.7V to AVDD, VREFIN = 2.4V to 5.5V, and digital inputs at VIO or GND
MIN NOM MAX UNIT
SPI TIMING REQUIREMENTS, FSDO = 0
f(SCLK) SCLK frequency 20 MHz
t(SCLKH) SCLK high time 20 ns
t(SCLKL) SCLK low time 23 ns
t(SDIS) SDI setup time 5 ns
t(SDIH) SDI hold time 8 ns
t(SDOTOZ) SDO active output to tri-state output delay 0 17 ns
t(SDOEN) SDO tri-state output to active output delay 0 21 ns
t(SDOTOD) SDO output delay 2 23 ns
t(CSS) CS setup time 15 ns
t(CSH) CS hold time 15 ns
t(CSHIGH) CS high time 15 ns
SPI TIMING REQUIREMENTS, FSDO = 1
f(SCLK) SCLK frequency (1) 30 MHz
t(SCLKH) SCLK high time 14 ns
t(SCLKL) SCLK low time 16 ns
t(SDIS) SDI setup time 5 ns
t(SDIH) SDI hold time 8 ns
t(SDOTOZ) SDO active output to tri-state output delay 0 17 ns
t(SDOEN) SDO tri-state output to active output delay 0 21 ns
t(SDOTOD) SDO output delay 2.5 30 ns
t(CSS) CS setup time 15 ns
t(CSH) CS hold time 15 ns
t(CSHIGH) CS high time 15 ns
(1) Write operations to the device can be performed at frequencies up to 50MHz.