JAJSUV8 June 2024 DAC80516
ADVANCE INFORMATION
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SPI TIMING REQUIREMENTS, FSDO = 0 | |||||
f(SCLK) | SCLK frequency | 20 | MHz | ||
t(SCLKH) | SCLK high time | 20 | ns | ||
t(SCLKL) | SCLK low time | 23 | ns | ||
t(SDIS) | SDI setup time | 5 | ns | ||
t(SDIH) | SDI hold time | 8 | ns | ||
t(SDOTOZ) | SDO active output to tri-state output delay | 0 | 17 | ns | |
t(SDOEN) | SDO tri-state output to active output delay | 0 | 21 | ns | |
t(SDOTOD) | SDO output delay | 2 | 23 | ns | |
t(CSS) | CS setup time | 15 | ns | ||
t(CSH) | CS hold time | 15 | ns | ||
t(CSHIGH) | CS high time | 15 | ns | ||
SPI TIMING REQUIREMENTS, FSDO = 1 | |||||
f(SCLK) | SCLK frequency | 30 | MHz | ||
t(SCLKH) | SCLK high time | 14 | ns | ||
t(SCLKL) | SCLK low time | 16 | ns | ||
t(SDIS) | SDI setup time | 5 | ns | ||
t(SDIH) | SDI hold time | 8 | ns | ||
t(SDOTOZ) | SDO active output to tri-state output delay | 0 | 17 | ns | |
t(SDOEN) | SDO tri-state output to active output delay | 0 | 21 | ns | |
t(SDOTOD) | SDO output delay | 2.5 | 30 | ns | |
t(CSS) | CS setup time | 15 | ns | ||
t(CSH) | CS hold time | 15 | ns | ||
t(CSHIGH) | CS high time | 15 | ns |