JAJSI27A October 2019 – December 2019 DAC11001A , DAC81001 , DAC91001
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Read/Write | Address | DAC-CLEAR-DATA (8 bits, left justified) | |||||||||||||
R/W | W | R/W | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
000h | 0h | ||||||||||||||
W | W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | Read/Write | R/W | N/A | Read when set to 1 or write when set to 0 |
30:24 | Address | W | N/A | 03h |
23:16 | DAC-CLEAR-DATA | R/W | 00h | Stores the 8-bit data to be loaded to DAC in left-justified, straight-binary format. DAC data registers updated with this value when CLR pin asserted low |
15:0 | 000h | W | N/A | N/A |