JAJSJH8A October 2020 – May 2021 DAC61402 , DAC81402
PRODUCTION DATA
Return to Register Map.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEMPALM-EN | DACBUSY-EN | CRCALM-EN | RESERVED | |||
R-0h | R/W-1h | R/W-0h | R/W-1h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEV-PWDWN | CRC-EN | RESERVED | SDO-EN | FSDO | RESERVED | |
R-1h | R-0h | R/W-1h | R/W-0h | R-0h | R/W-1h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved for factory use |
11 | TEMPALM-EN | R/W | 1h | When set to 1, a thermal alarm triggers the FAULT pin. |
10 | DACBUSY-EN | R/W | 0h | When set to 1, the FAULT pin is set between DAC output updates. Contrary to other alarm events, this alarm resets automatically. |
9 | CRCALM-EN | R/W | 1h | When set to 1, a CRC error triggers the FAULT pin.. |
8-6 | RESERVED | R | 2h | Reserved for factory use |
5 | DEV-PWDWN | R/W | 1h | DEV-PWDWN = 1 sets the device in
power-down mode. DEV-PWDWN = 0 sets the device in active mode. |
4 | CRC-EN | R/W | 0h | When set to 1, frame error checking is enabled. |
3 | RESERVED | R | 0h | Reserved for factory use |
2 | SDO-EN | R/W | 1h | When set to 1, the SDO pin is operational. |
1 | FSDO | R/W | 0h | Fast SDO bit (half-cycle speedup). When 0, SDO updates on SCLK rising edges. When 1, SDO updates on SCLK falling edges. |
0 | RESERVED | R | 0h | Reserved for factory use |