JAJS398F January 2009 – April 2018 DAC7568 , DAC8168 , DAC8568
PRODUCTION DATA.
The DAC7568, DAC8168, and DAC8568 contain a clear code register. The clear code register can be accessed via the serial peripheral interface (SPI) and is user-configurable. Bringing the CLR pin low clears the content of all DAC registers and all DAC buffers, and replaces the code with the code determined by the clear code register. The clear code register can be written to by applying the commands showed in Table 2. The control bits must be set as follows to access the clear code register that is programmed via the feature bits, F0 and F1: C3 = '0', C2 = '1', C1 = '0', and C0 = '1'. The default setting of the clear code register sets the output of all DAC channels to 0V when CLR pin is brought low. The CLR pin is falling-edge triggered; therefore, the device exits clear code mode on the 32nd falling edge of the next write sequence. If CLR pin is brought low during a write sequence, this write sequence is aborted and the DAC registers and DAC buffers are cleared as described previously.
When performing a software reset of the device, the clear code register is set back to its default mode (DB1 = DB0 = '0'). Setting the clear code register to DB1 = DB0 = '1' ignores any activity on the external CLR pin.