8.2.1 Loop-Powered 2-Wire 4-mA to 20-mA Transmitter With XTR116

Figure 33. Loop-Powered Transmitter

8.2.1.2 Detailed Design Procedure

Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides simplicity and improved performance due to the matched internal resistors. The output current can be modified if necessary by looking using Equation 2.

Equation 2.

For more details of this application, see 2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7). It covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.

8.2.1.3 Application Curves

Total unadjusted error (TUE) is a good estimate for the performance of the output as shown in Figure 34. The linearity of the output or INL is in Figure 35.

Figure 34. Total Unadjusted Error

Figure 35. Integral Nonlineareity

8.2.2 Bipolar Operation Using the DAC8551-Q1 Device

The DAC8551-Q1 device has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 36. The circuit shown gives an output voltage range of ±V_REF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.

Figure 36. Bipolar Output Range

The output voltage for any input code can be calculated as follows:

Equation 3.

where D represents the input code in decimal (0–65,535)

with V_REF = 5V, R₁ = R₂ = 10 kΩ.

Equation 4.

Using this example, an output voltage range of ±5 V with 0000h corresponding to a –5 V output and FFFFh corresponding to a 5 V output can be achieved. Similarly, using V_REF = 2.5 V, a ±2.5 V output voltage range can be achieved.

8.2.3 Using the REF02 As a Power Supply for the DACx551-Q1

Due to the extremely low supply current required by the DACx551-Q1, an alternative option is to use a precision reference such as the REF02 device to supply the required voltage to the device, as illustrated in Figure 37.

Figure 37. REF02 As a Power Supply to the DACx551-Q1

This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 device outputs a steady supply voltage for the device. If the REF02 device is used, the current it must supply to the device is 200 μA. This configuration is with no load on the output of the DAC. When a DAC output is loaded, the REF02 also must supply the current to the load.

The total current required (with a 5 kΩ load on the DAC output) is:

Equation 5.

The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2 mA current drawn from it. This value corresponds to a 3.9 LSB error.

8.3.1 Interface From the DACx551-Q1 to 8051

See Figure 38 for a serial interface between the DACx551-Q1 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DACx551-Q1, whereas RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data are to be transmitted to the DACx551-Q1, P3.3 is taken low. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DACx551-Q1 requires data with the MSB as the first bit received. Therefore, the 8051 transmit routine must take this into account, and mirror the data as needed.

Figure 38. Interface From the DACx551-Q1 to 80C51 or 80L51

8.3.2 Interface From the DACx551-Q1 to Microwire

Figure 39 shows an interface between the DACx551-Q1 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and is clocked into the DACx551-Q1 on the rising edge of the SK signal.

Figure 39. Interface From the DACx551-Q1 to Microwire

8.3.3 Interface From the DACx551-Q1 to 68HC11

Figure 40 shows a serial interface between the DACx551-Q1 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the DACx551-Q1, whereas the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.

Figure 40. Interface From the DACx551-Q1 to 68HC11

The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the DACx551-Q1, PC7 is left low after the first eight bits are transferred, then a second and third serial write operation are performed to the DAC. PC7 is taken high at the end of this procedure.