7.1 Overview

The DAC8551-Q1 and DAC6551-Q1 are small, low-power, voltage-output, 16- and 12-bit digital-to-analog converters (DACs) qualified for automotive applications. The DACx551-Q1 devices provide good linearity and minimize undesired code-to-code transient voltages. The devices use a versatile 3-wire serial interface that operates at clock rates to 30 MHz and is compatible with standard SPI, QSPI, Microwire, and digital signal processor (DSP) interfaces.

The DACx551-Q1 devices require an external reference voltage to set the output range. The devices incorporate a power-on-reset circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the device takes place. The devices contain a power-down feature, accessed over the serial interface, that reduces the current consumption to 800 nA at 5 V.

The DACx551-Q1 devices power consumption is only 800 µW at 5 V, reducing to less than 4 μW in power-down mode. The DACx551-Q1 devices are available in a VSSOP-8 package.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 DAC Section

The DACx551-Q1 architecture consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a block diagram of the DAC architecture.

Figure 27. DACx551-Q1 Architecture

The input coding to the DACx551-Q1 is straight binary, so the ideal output voltage is given by:

Equation 1.

where:

• n = resolution in bits; 12 (DAC6551-Q1) or 16 (DAC8551-Q1)
• D_IN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 2^n-1.

7.3.1.1 Resistor String

The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier.

Figure 28. Resistor String

7.3.1.2 Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to V_DD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.4 V/μs with a full-scale setting time of 8 μs with the output unloaded.

The inverting input of the output amplifier is brought out to the V_FB pin. This configuration allows for better accuracy in critical applications by tying the V_FB point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications.

7.4 Device Functional Modes

7.4.1 Power-Down Modes

The DACx551-Q1 supports four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of operation of the device.

Table 1. Operating Modes

PD1 (DB17)	PD0 (DB16)	OPERATING MODE
0	0	Normal operation
—	—	Power-down modes
0	1	Output typically 1 kΩ to GND
1	0	Output typically 100 kΩ to GND
1	1	High-Z

When both bits are set to 0, the device works normally with its typical current consumption of 160 μA at 5 V. However, for the three power-down modes, the supply current falls to 800 nA at 5 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This configuration has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options. The output is connected internally to GND through a 1‑kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z). The output stage is illustrated in Figure 29.

Figure 29. Output Stage During Power Down

All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power down. The time to exit power-down is typically 2.5 μs for V_DD = 5 V, and 5 μs for V_DD = 3 V. See the Typical Characteristics for more information.

7.5 Programming

The DAC8551-Q1 and DAC6551-Q1 devices have a 3-wire serial interface (SYNC, SCLK, and D_IN), which is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation Timing Diagram section for an example of a typical write sequence.

The input shift register is 24 bits wide, as shown in Figure 30 and Figure 31. The first six bits are don't care bits. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). A more complete description of the various modes is located in the Power-Down Modes section. The next 16 bits are the left aligned data bits. These bits are transferred to the DAC register on the 24th falling edge of SCLK.

The write sequence begins by bringing the SYNC line low. Data from the D_IN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the devices compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change in the mode of operation).

At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought high again just before the next write sequence.

Figure 32. SYNC Interrupt Facility