JAJSEH8C December 2006 – January 2018 DAC8560
PRODUCTION DATA.
The input shift register is 24 bits wide, as shown in Table 4. The first six bits must be 000000. The next two bits (PD1 and PD0) are control bits that set the desired mode of operation (normal mode or any one of three power-down modes) as indicated in Table 1.
A more complete description of the various modes is located in Power-Down Modes. The next 16 bits are the data bits, which are transferred to the DAC register on the 24th falling edge of SCLK under normal operation (see Table 1).