DACxx6x-Q1 Automotive Dual 16-, 14-, 12-Bit, Low-Power, Buffered, Voltage-Output DACs With 2.5-V, 4-PPM/°C Internal Reference

1 Features

• Qualified for Automotive Applications
• AEC-Q100 Qualified with the Following Results:
  • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
  • Device HBM ESD Classification Level 2
  • Device CDM ESD Classification Level C4B
• Relative Accuracy:
  • DAC756x (12-Bit): 0.3 LSB INL
  • DAC816x (14-Bit): 1 LSB INL
  • DAC856x (16-Bit): 4 LSB INL
• Glitch Impulse: 0.1 nV-s
• Bidirectional Reference: Input or 2.5-V Output
  • Output Disabled by Default
  • ±5-mV Initial Accuracy (Max)
  • 4-ppm/°C Temperature Drift (Typ)
  • 10-ppm/°C Temperature Drift (Max)
  • 20-mA Sink and Source Capability
• Power-On Reset to Zero Scale or Mid-Scale
• Low-Power: 4 mW (Typ, 5-V AV_DD, Including Internal Reference Current)
• Wide Power-Supply Range: 2.7 V to 5.5 V
• 50-MHz SPI With Schmitt-Triggered Inputs
• LDAC and CLR Functions
• Output Buffer With Rail-to-Rail Operation
• Package: VSSOP-10

2 Applications

• Portable Instrumentation
• PLC Analog Output Module
• Closed-Loop Servo Control
• Voltage Controlled Oscillator Tuning
• Data Acquisition Systems
• Programmable Gain and Offset Adjustment

3 Description

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 (DACxx6x-Q1) devices are low-power, voltage-output, dual-channel, 12-, 14-, and 16-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the V_REFIN/V_REFOUT pin.

These devices are monotonic, providing excellent linearity and minimizing undesired code-to-code transient voltages (glitch). They use a versatile three-wire serial interface that operates at clock rates up to 50 MHz. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACxx62-Q1 devices incorporate a power-on-reset circuit that ensures the DAC output powers up and remains at zero scale until a valid code is written to the device, whereas the DACxx63-Q1 devices similarly power up at mid-scale. These devices contain a power-down feature that reduces current consumption to typically 550 nA at 5 V. The low power consumption, internal reference, and small footprint make these devices ideal for portable, battery-operated equipment.

The DACxx62-Q1 devices are drop-in and function-compatible with each device in this family, as are the DACxx63-Q1 devices. The entire family is available in a 10-pin VSSOP-10 (DGS) package.

1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

4 Revision History

Changes from * Revision (May 2013) to A Revision

• Changed Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
• Released the DAC8563-Q1, DAC8162-Q1, DAC8163-Q1, DAC7562-Q1, and DAC7563-Q1 devicesGo
• Added the code-change total glitch amplitude parameter to the Electrical Characteristics table Go

5 Device Comparison Table

6 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

7 Specifications

1. Asynchronous LDAC update mode. For more information, see the LDAC Functionality section.

2. Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.

Figure 1. Serial Write Operation

7.7 Typical Characteristics

7.7.1 Tables of Graphs

Table 1. Typical Characteristics: Internal Reference Performance

MEASUREMENT		POWER-SUPPLY VOLTAGE	FIGURE NUMBER
Internal Reference Voltage vs Temperature		5.5 V	Figure 2
Internal Reference Voltage Temperature Drift Histogram			Figure 3
Internal Reference Voltage vs Load Current			Figure 4
Internal Reference Voltage vs Time			Figure 5
Internal Reference Noise Density vs Frequency			Figure 6
Internal Reference Voltage vs Supply Voltage		2.7 V – 5.5 V	Figure 7

Table 2. Typical Characteristics: DAC Static Performance

MEASUREMENT		POWER-SUPPLY VOLTAGE	FIGURE NUMBER
FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS
Full-Scale Error vs Temperature		5.5 V	Figure 16
Gain Error vs Temperature			Figure 17
Offset Error vs Temperature			Figure 18
Zero-Code Error vs Temperature			Figure 19
Full-Scale Error vs Temperature		2.7 V	Figure 63
Gain Error vs Temperature			Figure 64
Offset Error vs Temperature			Figure 65
Zero-Code Error vs Temperature			Figure 66
LOAD REGULATION
DAC Output Voltage vs Load Current		5.5 V	Figure 30
		2.7 V	Figure 74
DIFFERENTIAL NONLINEARITY ERROR
Differential Linearity Error vs Digital Input Code	T = –40°C	5.5 V	Figure 9
	T = 25°C		Figure 11
	T = 125°C		Figure 13
Differential Linearity Error vs Temperature			Figure 15
Differential Linearity Error vs Digital Input Code	T = –40°C	2.7 V	Figure 56
	T = 25°C		Figure 58
	T = 125°C		Figure 60
Differential Linearity Error vs Temperature			Figure 62
INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY)
Linearity Error vs Digital Input Code	T = –40°C	5.5 V	Figure 8
	T = 25°C		Figure 10
	T = 125°C		Figure 12
Linearity Error vs Temperature			Figure 14
Linearity Error vs Digital Input Code	T = –40°C	2.7 V	Figure 55
	T = 25°C		Figure 57
	T = 125°C		Figure 59
Linearity Error vs Temperature			Figure 61
POWER-DOWN CURRENT
Power-Down Current vs Temperature		5.5 V	Figure 28
Power-Down Current vs Power-Supply Voltage		2.7 V – 5.5 V	Figure 29
Power-Down Current vs Temperature		2.7 V	Figure 73
POWER-SUPPLY CURRENT
Power-Supply Current vs Temperature	External VREF	5.5 V	Figure 20
	Internal VREF		Figure 21
Power-Supply Current vs Digital Input Code	External VREF		Figure 22
	Internal VREF		Figure 23
Power-Supply Current Histogram	External VREF		Figure 24
	Internal VREF		Figure 25
Power-Supply Current vs Power-Supply Voltage	External VREF	2.7 V – 5.5 V	Figure 26
	Internal VREF		Figure 27
Power-Supply Current vs Temperature	External VREF	3.6 V	Figure 49
	Internal VREF		Figure 50
Power-Supply Current vs Digital Input Code	External VREF		Figure 51
	Internal VREF		Figure 52
Power-Supply Current Histogram	External VREF		Figure 53
	Internal VREF		Figure 54
Power-Supply Current vs Temperature	External VREF	2.7 V	Figure 67
	Internal VREF		Figure 68
Power-Supply Current vs Digital Input Code	External VREF		Figure 69
	Internal VREF		Figure 70
Power-Supply Current Histogram	External VREF		Figure 71
	Internal VREF		Figure 72

Table 3. Typical Characteristics: DAC Dynamic Performance

MEASUREMENT		POWER-SUPPLY VOLTAGE	FIGURE NUMBER
CHANNEL-TO-CHANNEL CROSSTALK
Channel-to-Channel Crosstalk	5-V Rising Edge	5.5 V	Figure 43
	5-V Falling Edge		Figure 44
CLOCK FEEDTHROUGH
Clock Feedthrough	500 kHz, Mid-Scale	5.5 V	Figure 48
		2.7 V	Figure 87
GLITCH IMPULSE
Glitch Impulse, 1-LSB Step	Rising Edge, Code 7FFFh to 8000h	5.5 V	Figure 37
	Falling Edge, Code 8000h to 7FFFh		Figure 38
Glitch Impulse, 4-LSB Step	Rising Edge, Code 7FFCh to 8000h		Figure 39
	Falling Edge, Code 8000h to 7FFCh		Figure 40
Glitch Impulse, 16-LSB Step	Rising Edge, Code 7FF0h to 8000h		Figure 41
	Falling Edge, Code 8000h to 7FF0h		Figure 42
Glitch Impulse, 1-LSB Step	Rising Edge, Code 7FFFh to 8000h	2.7 V	Figure 79
	Falling Edge, Code 8000h to 7FFFh		Figure 80
Glitch Impulse, 4-LSB Step	Rising Edge, Code 7FFCh to 8000h		Figure 81
	Falling Edge, Code 8000h to 7FFCh		Figure 82
Glitch Impulse, 16-LSB Step	Rising Edge, Code 7FF0h to 8000h		Figure 83
	Falling Edge, Code 8000h to 7FF0h		Figure 84
NOISE
DAC Output Noise Density vs Frequency	External VREF	5.5 V	Figure 45
	Internal VREF		Figure 46
DAC Output Noise 0.1 Hz to 10 Hz	External VREF		Figure 47
POWER-ON GLITCH
Power-on Glitch	Reset to Zero Scale	5.5 V	Figure 35
	Reset to Mid-Scale		Figure 36
	Reset to Zero Scale	2.7 V	Figure 85
	Reset to Mid-Scale		Figure 86
SETTLING TIME
Full-Scale Settling Time	Rising Edge, Code 0h to FFFFh	5.5 V	Figure 31
	Falling Edge, Code FFFFh to 0h		Figure 32
Half-Scale Settling Time	Rising Edge, Code 4000h to C000h		Figure 33
	Falling Edge, Code C000h to 4000h		Figure 34
Full-Scale Settling Time	Rising Edge, Code 0h to FFFFh	2.7 V	Figure 75
	Falling Edge, Code FFFFh to 0h		Figure 76
Half-Scale Settling Time	Rising Edge, Code 4000h to C000h		Figure 77
	Falling Edge, Code C000h to 4000h		Figure 78

7.7.2 Internal Reference

At T_A = 25°C, AV_DD = 5.5 V, gain = 2 and V_REFOUT, unloaded unless otherwise noted.

Figure 2. Internal Reference Voltage vs Temperature

Figure 4. Internal Reference Voltage vs Load Current

Figure 6. Internal Reference Noise Density vs Frequency

Figure 3. Internal Reference Voltage Temperature Drift Histogram

Figure 5. Internal Reference Voltage vs Time

Figure 7. Internal Reference Voltage vs Supply Voltage

7.7.3 DAC at AV_DD = 5.5 V

At T_A = 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

Figure 8. Linearity Error vs Digital Input Code (–40°C)

Figure 10. Linearity Error vs Digital Input Code (25°C)

Figure 12. Linearity Error vs Digital Input Code (125°C)

Figure 14. Linearity Error vs Temperature

Figure 16. Full-Scale Error vs Temperature

Figure 18. Offset Error vs Temperature

Figure 20. Power-supply Current vs Temperature

Figure 22. Power-Supply Current vs Digital Input Code

Figure 24. Power-Supply Current Histogram

Figure 26. Power-Supply Current vs Power-Supply Voltage

Figure 28. Power-Down Current vs Temperature

Figure 30. DAC Output Voltage vs Load Current

Figure 32. Full-Scale Settling Time: Falling Edge

Figure 34. Half-Scale Settling Time: Falling Edge

Figure 36. Power-On Glitch Reset to Mid-Scale

Figure 38. Glitch Impulse Falling Edge, 1-LSB Step

Figure 40. Glitch Impulse Falling Edge, 4-LSB Step

Figure 42. Glitch Impulse Falling Edge, 16-LSB Step

Figure 44. Channel-to-Channel Crosstalk 5-V Falling Edge

Figure 46. DAC Output Noise Density vs Frequency

Figure 48. Clock Feedthrough 500 kHz, Mid-Scale

Figure 9. Differential Linearity Error vs Digital Input Code (–40°C)

Figure 11. Differential Linearity Error vs Digital Input Code (25°C)

Figure 13. Differential Linearity Error vs Digital Input Code (125°C)

Figure 15. Differential Linearity Error vs Temperature

Figure 17. Gain Error vs Temperature

Figure 19. Zero-code Error vs Temperature

Figure 21. Power-supply Current vs Temperature

Figure 23. Power-Supply Current vs Digital Input Code

Figure 25. Power-Supply Current Histogram

Figure 27. Power-Supply Current vs Power-Supply Voltage

Figure 29. Power-Down Current vs Power-Supply Voltage

Figure 31. Full-Scale Settling Time: Rising Edge

Figure 33. Half-Scale Settling Time: Rising Edge

Figure 35. Power-On Glitch Reset to Zero Scale

Figure 37. Glitch Impulse Rising Edge, 1-LSB Step

Figure 39. Glitch Impulse Rising Edge, 4-LSB Step

Figure 41. Glitch Impulse Rising Edge, 16-LSB Step

Figure 43. Channel-to-Channel Crosstalk 5-V Rising Edge

Figure 45. DAC Output Noise Density vs Frequency

Figure 47. DAC Output Noise 0.1 Hz TO 10 Hz

7.7.4 Typical Characteristics: DAC at AV_DD = 3.6 V

At T_A = 25°C, 3.3-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

Figure 49. Power-Supply Current vs Temperature

Figure 51. Power-Supply Current vs Digital Input Code

Figure 53. Power-Supply Current Histogram

Figure 50. Power-Supply Current vs Temperature

Figure 52. Power-Supply Current vs Digital Input Code

Figure 54. Power-Supply Current Histogram

7.7.5 Typical Characteristics: DAC at AV_DD = 2.7 V

At T_A = 25°C, 2.5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

Figure 55. Linearity Error vs Digital Input Code (–40°C)

Figure 57. Linearity Error vs Digital Input Code (25°C)

Figure 59. Linearity Error vs Digital Input Code (125°C)

Figure 61. Linearity Error vs Temperature

Figure 63. Full-Scale Error vs Temperature

Figure 65. Offset Error vs Temperature

Figure 67. Power-Supply Current vs Temperature

Figure 69. Power-Supply Current vs Digital Input Code

Figure 71. Power-Supply Current Histogram

Figure 73. Power-Down Current vs Temperature

Figure 75. Full-Scale Settling Time: Rising Edge

Figure 77. Half-Scale Settling Time: Rising Edge

Figure 79. Glitch Impulse Rising Edge, 1-LSB Step

Figure 81. Glitch Impulse Rising Edge, 4-LSB Step

Figure 83. Glitch Impulse Rising Edge, 16-LSB Step

Figure 85. Power-On Glitch Reset to Zero Scale

Figure 87. Clock Feedthrough 500 kHz, Mid-Scale

Figure 56. Differential Linearity Error vs Digital Input Code (–40°C)

Figure 58. Differential Linearity Error vs Digital Input Code (25°C)

Figure 60. Differential Linearity Error vs Digital Input Code (125°C)

Figure 62. Differential Linearity Error vs Temperature

Figure 64. Gain Error vs Temperature

Figure 66. Zero-Code Error vs Temperature

Figure 68. Power-Supply Current vs Temperature

Figure 70. Power-Supply Current vs Digital Input Code

Figure 72. Power-Supply Current Histogram

Figure 74. DAC Output Voltage vs Load Current

Figure 76. Full-Scale Settling Time: Falling Edge

Figure 78. Half-Scale Settling Time: Falling Edge

Figure 80. Glitch Impulse Falling Edge, 1-LSB Step

Figure 82. Glitch Impulse Falling Edge, 4-LSB Step

Figure 84. Glitch Impulse Falling Edge, 16-LSB Step

Figure 86. Power-On Glitch Reset to Mid-Scale