JAJS398F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Electrical Characteristics
    3. 8.3 Timing Requirements
    4. 8.4 Typical Characteristics: Internal Reference
    5. 8.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 8.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 8.7 Typical Characteristics: DAC at AVDD = 2.7 V
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Digital-to-Analog Converter (DAC)
      2. 9.2.2  Resistor String
      3. 9.2.3  Output Amplifier
      4. 9.2.4  Internal Reference
      5. 9.2.5  Serial Interface
      6. 9.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 9.2.7  SYNC Interrupt
      8. 9.2.8  Power-on Reset to Zero Scale or Midscale
      9. 9.2.9  Clear Code Register and CLR Pin
      10. 9.2.10 Software Reset Function
      11. 9.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 9.3 Device Functional Modes
      1. 9.3.1 Enable/Disable Internal Reference
        1. 9.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 9.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 9.3.2 LDAC Functionality
      3. 9.3.3 Power-Down Modes
        1. 9.3.3.1 DAC Power-Down Commands
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications - Microprocessor Interfacing
      1. 10.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Internal Reference
            1. 10.2.1.1.1.1 Supply Voltage
            2. 10.2.1.1.1.2 Temperature Drift
            3. 10.2.1.1.1.3 Noise Performance
            4. 10.2.1.1.1.4 Load Regulation
            5. 10.2.1.1.1.5 Long-Term Stability
            6. 10.2.1.1.1.6 Thermal Hysteresis
          2. 10.2.1.1.2 DAC Noise Performance
          3. 10.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 10.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 10.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
        1. 12.1.1.1 静的特性
          1. 12.1.1.1.1  分解能
          2. 12.1.1.1.2  最下位ビット(LSB)
          3. 12.1.1.1.3  最上位ビット(MSB)
          4. 12.1.1.1.4  相対精度または積分非直線性(INL)
          5. 12.1.1.1.5  微分非直線性(DNL)
          6. 12.1.1.1.6  フルスケール誤差
          7. 12.1.1.1.7  オフセット誤差
          8. 12.1.1.1.8  ゼロ・コード誤差
          9. 12.1.1.1.9  ゲイン誤差
          10. 12.1.1.1.10 フルスケール誤差ドリフト
          11. 12.1.1.1.11 オフセット誤差ドリフト
          12. 12.1.1.1.12 ゼロ・コード誤差ドリフト
          13. 12.1.1.1.13 ゲイン温度係数
          14. 12.1.1.1.14 電源除去率(PSRR)
          15. 12.1.1.1.15 単調性
        2. 12.1.1.2 動的特性
          1. 12.1.1.2.1  スルー・レート
          2. 12.1.1.2.2  出力電圧のセトリング時間
          3. 12.1.1.2.3  コード変化/デジタル-アナログ・グリッチ・エネルギー
          4. 12.1.1.2.4  デジタル・フィードスルー
          5. 12.1.1.2.5  チャネル間DCクロストーク
          6. 12.1.1.2.6  チャネル間ACクロストーク
          7. 12.1.1.2.7  信号対雑音比(SNR)
          8. 12.1.1.2.8  全高調波歪み(THD)
          9. 12.1.1.2.9  スプリアスフリー・ダイナミック・レンジ(SFDR)
          10. 12.1.1.2.10 信号対雑音比+歪み(SINAD)
          11. 12.1.1.2.11 DAC出力ノイズ密度
          12. 12.1.1.2.12 DAC出力ノイズ
          13. 12.1.1.2.13 フルスケール範囲(FSR)
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface

Figure 125 shows a serial interface between the DAC7568, DAC8168, and DAC8568 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC7568, DAC8168, or DAC8568, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051; in this case, port line P3.3 is used. When data are to be transmitted to the DAC7568, DAC8168, and DAC8568, P3.3 is taken low. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DAC7568, DAC8168, and DAC8568 require the data with the MSB as the first bit received. Therefore, the 8051 transmit routine must take this requirement into account, and mirror the data as needed.

DAC7568 DAC8168 DAC8568 interf_80c51_bas430.gifFigure 125. DAC7568/DAC8168/DAC8568 to 80C51/80L51 Interface