JAJSE97D June 2017 – May 2019 DAC8740H , DAC8741H
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SPI TIMING | SPI TIMING | SPI TIMING | SPI TIMING | SPI TIMING | SPI TIMING |
tc | SCLK cycle time | 80 | ns | ||
tw1 | SCLK high time | 32 | ns | ||
tw2 | SCLK low time | 32 | ns | ||
tsu | CS to SCLK falling edge setup time | 32 | ns | ||
tsu1 | Data setup time | 5 | ns | ||
th1 | Data hold time | 5 | ns | ||
td1 | SCLK falling edge to CS rising edge | 32 | ns | ||
tw3 | Minimum CS high time (1) | 3.06 | us | ||
tv | SCLK rising edge to SDO valid | 32 | ns | ||
trst | Reset low time | 100 | ns | ||
HART MODE TIMING | |||||
tcstart | Carrier start time. Time from RTS falling edge to transmit carrier reaching its first peak. | 5 | Bit-Times | ||
tcstop | Carrier stop time. Time from RTS rising edge to transmit carrier amplitude falling below the receive amplitude. | 3 | Bit-Times | ||
tcdecay | Carrier decay time. Time from RTS riding edge to carrier amplitude dropping to zero. | 6 | Bit-Times | ||
tcdeton | Carrier detect on. Time from valid carrier on receive path to CD rising edge. | 6 | Bit-Times | ||
tcdetoff1 | Carrier detect off. Time from valid carrier removed on receive path to CD falling edge. | 3 | ms | ||
tcdetoff2 | Carrier detect on when transitioning from transmit mode to receive mode in the presence of a constant valid receive carrier. | 2.1 | ms | ||
tcos1 | Crystal oscillator power-up time from enabling the oscillator via clock configuration pins with 16-pF load capacitors. | 25 | ms | ||
tcos2 | Crystal oscillator power-up time from enabling the oscillator via clock configuration pins with 36-pF load capacitors. | 25 | ms | ||
tref | Reference power-up time from enabling via hardware pin. | 10 | ms | ||
tpow | Transition time from power-down mode to normal operating mode with external clock and external reference. | 30 | µs |