JAJSCW9 February   2017 DAC8775

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. 8.3.3.1 Buck-Boost Converters Outputs
        2. 8.3.3.2 Selecting and Enabling Buck-Boost Converters
        3. 8.3.3.3 Configurable Clamp Feature and Current Output Settling Time
          1. 8.3.3.3.1 Default Mode - CCLP[1:0] = "00" - Current Output Only
          2. 8.3.3.3.2 Fixed Clamp Mode - CCLP[1:0] = "01" - Current and Voltage Output
          3. 8.3.3.3.3 Auto Learn Mode - CCLP[1:0] = "10" - Current Output Only
          4. 8.3.3.3.4 High Side Clamp (HSCLMP)
        4. 8.3.3.4 Buck-Boost Converters and Open Circuit Current Output
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD Bits
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. 8.4.1.1 Stand-Alone Operation
        2. 8.4.1.2 Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. 8.4.5.1 Asynchronous Mode
        2. 8.4.5.2 Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. 8.4.9.1 DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 DAC8775 Commands
      2. 8.5.2 Register Maps and Bit Functions
        1. 8.5.2.1  No Operation Register (address = 0x00) [reset = 0x0000]
        2. 8.5.2.2  Reset Register (address = 0x01) [reset = 0x0000]
        3. 8.5.2.3  Reset Config Register (address = 0x02) [reset = 0x0000]
        4. 8.5.2.4  Select DAC Register (address = 0x03) [reset = 0x0000]
        5. 8.5.2.5  Configuration DAC Register (address = 0x04) [reset = 0x0000]
        6. 8.5.2.6  DAC Data Register (address = 0x05) [reset = 0x0000]
        7. 8.5.2.7  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
        8. 8.5.2.8  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
        9. 8.5.2.9  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
        10. 8.5.2.10 DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
        11. 8.5.2.11 DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
        12. 8.5.2.12 Status Register (address = 0x0B) [reset = 0x1000]
        13. 8.5.2.13 Status Mask Register (address = 0x0C) [reset = 0x0000]
        14. 8.5.2.14 Alarm Action Register (address = 0x0D) [reset = 0x0000]
        15. 8.5.2.15 User Alarm Code Register (address = 0x0E) [reset = 0x0000]
        16. 8.5.2.16 Reserved Register (address = 0x0F) [reset = N/A]
        17. 8.5.2.17 Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
        18. 8.5.2.18 Device ID Register (address = 0x11) [reset = 0x0000]
        19. 8.5.2.19 Reserved Register (address 0x12 - 0xFF) [reset = N/A]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Ouputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling time with Auto learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8775
    2. 9.2 Typical Application
      1. 9.2.1 1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RWF Package
72-Pin VQFN
Top View
1. Thermal pad should be connected to ground.

Pin Functions

PIN DESCRIPTION
NAME NO.
PVDD_D 1 Buck-Boost Converter power switch supply D
LP_D 2 External Inductor terminal - positive D
PVSS_D 3 Ground for Buck-Boost converter switches D
LN_D 4 External Inductor terminal - negative D
PVDD_C 5 Buck-Boost Converter power switch supply C
LP_C 6 External Inductor terminal - positive C
PVSS_C 7 Ground for Buck-Boost converter switches C
LN_C 8 External Inductor terminal - negative C
DCDC_AGND_AB 9 Analog GND Buck-Boost converter Channels A and B
LN_B 10 External Inductor terminal - negative B
PVSS_B 11 Ground for Buck-Boost converter switches B
LP_B 12 External Inductor terminal - positive B
PVDD_B 13 Buck-Boost Converter power switch supply B
LN_A 14 External Inductor terminal - negative A
PVSS_A 15 Ground for Buck-Boost converter switches A
LP_A 16 External Inductor terminal - positive A
PVDD_A 17 Buck-Boost Converter power switch supply A
PBKG 18 Chip substrate, connect to 0 V
VNEG_IN_A 19 Negative power supply for VOUT_A and IOUT_A
VNEG_IN_B 20 Negative power supply for VOUT_B and IOUT_A
SCLK 21 Serial clock input of serial peripheral interface (SPI™). Data can be transferred at rates up to 25 MHz. Schmitt-Trigger logic input.
SDIN 22 Serial data input. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. Schmitt-Trigger logic input.
LDAC 23 Load DAC latch control input. A logic low on this pin loads the input shift register data into the DAC register and updates the DAC output.
SDO 24 Serial data output. Data are valid on the falling edge of SCLK.
SYNC 25 SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high, SDO is in high-impedance status.
CLR 26 Level Triggered clear pin (Active High). Clears all DAC channel to zero code or mid code (see DAC clear section)
HARTIN_B 27 Input pin for HART modulation. for IOUT_B
CCOMP_B 28 External compensation capacitor connection pin for VOUT_B . Addition of the external capacitor improves the stability with high capacitive loads at the VOUT_B pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
HARTIN_A 29 Input pin for HART modulation. for IOUT_A
CCOMP_A 30 External compensation capacitor connection pin for VOUT_A . Addition of the external capacitor improves the stability with high capacitive loads at the VOUT_A pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
VSENSEP_B 31 Sense output pin for the positive voltage output (channel B) load connection.
VSENSEN_B 32 Sense output pin for the negative voltage output (channel B) load connection.
VSENSEP_A 33 Sense output pin for the positive voltage output (channel A) load connection.
VSENSEN_A 34 Sense output pin for the negative voltage output (channel A) load connection.
DAC_AGND_AB 35 Analog GND DAC Channels A and B
VNEG_IN_A 36 Negative power supply for VOUT_A and IOUT_A
IOUT_A 37 Current Output Pin (Channel A)
VPOS_IN_A 38 Positive power supply for VOUT_A and IOUT_A
VOUT_A 39 Voltage Output Pin (Channel A)
VNEG_IN_B 40 Negative power supply for VOUT_B and IOUT_B
IOUT_B 41 Current Output Pin (Channel B)
VPOS_IN_B 42 Positive power supply for VOUT_B and IOUT_B
VOUT_B 43 Voltage Output Pin (Channel B)
AVDD 44 Power supply for all analog circuitry of the device except buck-boost converters and output amplifiers
REFGND 45 Reference ground
REFIN 46 Reference input
REFOUT 47 Internal reference output. Connects to REFIN when using internal reference.
VOUT_C 48 Voltage Output Pin (Channel C)
VPOS_IN_C 49 Positive power supply for VOUT_C and IOUT_C
IOUT_C 50 Current Output Pin (Channel C)
VNEG_IN_C 51 Negative power supply for VOUT_C and IOUT_C
VOUT_D 52 Voltage Output Pin (Channel D)
VPOS_IN_D 53 Positive power supply for VOUT_D and IOUT_D
IOUT_D 54 Current Output Pin (Channel D)
VNEG_IN_D 55 Negative power supply for VOUT_D and IOUT_D
DAC_AGND_CD 56 Analog GND DAC Channels C and D
VSENSEN_D 57 Sense output pin for the negative voltage output (channel D) load connection.
VSENSEP_D 58 Sense output pin for the positive voltage output (channel D) load connection.
VSENSEN_C 59 Sense output pin for the negative voltage output (channel C) load connection.
VSENSEP_C 60 Sense output pin for the positive voltage output (channel C) load connection.
CCOMP_D 61 External compensation capacitor connection pin for VOUT_D . Addition of the external capacitor improves the stability with high capacitive loads at the VOUT_D pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
HARTIN_D 62 Input pin for HART modulation. for IOUT_D
CCOMP_C 63 External compensation capacitor connection pin for VOUT_C . Addition of the external capacitor improves the stability with high capacitive loads at the VOUT_C pin by reducing the bandwidth of the output amplifier at the expense of increased settling time.
HARTIN_C 64 Input pin for HART modulation. for IOUT_C
DVDD_EN 65 Internal power-supply enable pin. Connect this pin to PBKG to disable the internal DVDD, or leave this pin unconnected to enable the internal DVDD. When this pin is connected to PBKG, an external supply must be connected to the DVDD pin.
DVDD 66 Digital Supply pin (Input/Output) Internal DVDD enabled when DVDD_EN is floating, External DVDD must be supplied when DVDD_EN is connected to PBKG
ALARM 67 ALARM pin. Open drain output. External pull-up resistor required (10 kΩ). The pin goes low (active) when the ALARM condition is detected on any of the outputs (OUT_A through OUT_D) (open circuit, over temperature, watchdog timeout, and others).
RESET 68 Reset input (active low). Logic low on this pin causes the device to perform a reset. A hardware reset must be issued using this pin after power up.
PBKG 69 Chip substrate, connect to 0 V
VNEG_IN_C 70 Negative power supply for VOUT_C
VNEG_IN_D 71 Negative power supply for VOUT_D
DCDC_AGND_CD 72 Analog GND Buck-Boost converter Channels C and D