JAJSI27A October   2019  – December 2019 DAC11001A , DAC81001 , DAC91001

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
      2.      高精度の制御ループ回路
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1      Absolute Maximum Ratings
    2. 8.2      ESD Ratings
    3. 8.3      Recommended Operating Conditions
    4. 8.4      Thermal Information Package
    5. 8.5      Electrical Characteristics
    6. Table 1. Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V
    7. Table 2. Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V
    8. Table 3. Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V
    9. Table 4. Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V
    10. 8.6      Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter Architecture
      2. 9.3.2 External Reference
      3. 9.3.3 Output Buffers
      4. 9.3.4 Internal Power-On Reset (POR)
      5. 9.3.5 Temperature Drift and Calibration
      6. 9.3.6 DAC Output Deglitch Circuit
    4. 9.4 Device Functional Modes
      1. 9.4.1 Fast-Settling Mode and THD
      2. 9.4.2 DAC Update Rate Mode
    5. 9.5 Programming
      1. 9.5.1 Daisy-Chain Operation
      2. 9.5.2 CLR Pin Functionality and Software Clear
      3. 9.5.3 Output Update (Synchronous and Asynchronous)
        1. 9.5.3.1 Synchronous Update
        2. 9.5.3.2 Asynchronous Update
      4. 9.5.4 Software Reset Mode
    6. 9.6 Register Map
      1. 9.6.1 NOP Register (address = 00h) [reset = 0x000000h]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]
        1. Table 10. DAC-DATA Register Field Descriptions
      3. 9.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]
        1. Table 11. CONFIG1 Register Field Descriptions
      4. 9.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]
        1. Table 12. DAC-CLEAR-DATA Register Field Descriptions
      5. 9.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]
        1. Table 13. TRIGGER Register Field Descriptions
      6. 9.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]
        1. Table 14. STATUS Register Field Descriptions
      7. 9.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]
        1. Table 15. CONFIG2 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Source Measure Unit (SMU)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Battery Test Equipment (BTE)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 High-Precision Control Loop
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Arbitrary Waveform Generation (AWG)
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
        3. 10.2.4.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Interfacing to a Processor
      2. 10.3.2 Interfacing to a Low-Jitter LDAC Source
      3. 10.3.3 Embedded Resistor Configurations
        1. 10.3.3.1 Minimizing Bias Current Mismatch
        2. 10.3.3.2 2x Gain configuration
        3. 10.3.3.3 Generating Negative Reference
    4. 10.4 What to Do and What Not to Do
      1. 10.4.1 What to Do
      2. 10.4.2 What Not to Do
    5. 10.5 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 サポート・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.4 Internal Power-On Reset (POR)

The DACx1001 incorporate two internal POR circuits for the DVDD, AVDD, IOVDD, VCC, and VSS supplies. The POR signals are ANDed together, so that all supplies must be at the minimal specified values for the device to not be in a reset condition. These POR circuits initialize internal registers, as well as set the analog outputs to a known state while the device supplies are ramping. All registers are reset to default values. The DACx1001 power on with the DAC registers set to zero scale. The DAC can be powered down by writing 1 to PDN (bit 4, address 02h). Typically, the POR function can be ignored as long as the device supplies power up and maintain the specified minimum voltage levels. However, in the case of supply drop or brownout, the DACx1001 can have an internal POR reset event. Figure 45 represents the internal POR threshold levels for the DVDD, AVDD, IOVDD, VCC, and VSS supplies.

DAC11001A DAC91001 DAC81001 SLASEL0_IPOR.gifFigure 45. Relevant Voltage Levels for the POR Circuit

For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply minimum) to 5.5 V (supply maximum). For a DVDD supply region between 2.5 V (undefined operation threshold) and 1.6 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a DVDD supply less than 1.6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 1.6 V for approximately 1 ms.

For the AVDD supply, no internal POR occurs for nominal supply operation from 4.5 V (supply minimum) to 5.5 V (supply maximum). For an AVDD supply region between 4.1 V (undefined operation threshold) and 3.3 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an AVDD supply less than 3.3 V (POR threshold), the internal POR resets as long as the supply voltage is less than 3.3 V for approximately 1 ms.

For the VCC supply, no internal POR occurs for nominal supply operation from 8 V (supply minimum) to 36 V (supply maximum). For VCC supply voltages between 7.5 V (undefined operation threshold) to 6 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a VCC supply less than 6 V (POR threshold), the internal POR resets as long as the supply voltage is less than 6 V for approximately 1 ms.

For the VSS supply, no internal POR occurs for nominal supply operation from –3 V (supply minimum) to –18 V (supply maximum). For VSS supply voltages between –2.7 V (undefined operation threshold) to –1.8 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For a VSS supply greater than –1.8 V (POR threshold), the internal POR resets as long as the supply voltage is higher than –1.8 V for approximately 1 ms.

For the IOVDD supply, no internal POR occurs for nominal supply operation from 1.8 V (supply minimum) to 5.5 V (supply maximum). For IOVDD supply voltages between 1.5 V (undefined operation threshold) and 0.8 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an IOVDD supply less than 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is less than 0.8 V for approximately 1 ms.

In case the DVDD, AVDD, IOVDD, VCC, or VSS supply drops to a level where the internal POR signal is indeterminate, power cycle the device followed using a software reset.