JAJS017N March 2000 – April 2020 DCP020503 , DCP020505 , DCP020507 , DCP020509 , DCP020515D , DCP021205 , DCP021212 , DCP021212D , DCP021515 , DCP022405 , DCP022405D , DCP022415D
PRODUCTION DATA
Any of the DCP02 series devices can be disabled or enabled by driving the SYNC pin using an open drain CMOS gate. If the SYNC pin is pulled low, the DCP02 becomes disabled. The disable time depends upon the external loading. The internal disable function is implemented in 2 μs. Removal of the pull down causes the DCP02 to be enabled.
Capacitive loading on the SYNC pin should be minimized (≤ 3 pF) in order to prevent a reduction in the oscillator frequency. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters describes disable/enable control circuitry.