JAJSD60 April   2017 DCPA10505 , DCPA10505D , DCPA10512 , DCPA10512D , DCPA10515 , DCPA10515D

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Electrical Characteristics
    5. 6.5  Switching Characteristics
    6. 6.6  Typical Characteristics (DCPA10505)
    7. 6.7  Typical Characteristics (DCPA10512)
    8. 6.8  Typical Characteristics (DCPA10515)
    9. 6.9  Typical Characteristics (DCPA10505D)
    10. 6.10 Typical Characteristics (DCPA10512D)
    11. 6.11 Typical Characteristics (DCPA10515D)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Isolation
        1. 7.3.1.1 Operation or Functional Isolation
        2. 7.3.1.2 Basic or Enhanced Isolation
        3. 7.3.1.3 Continuous Voltage
        4. 7.3.1.4 Isolation Voltage
        5. 7.3.1.5 Repeated High-Voltage Isolation Testing
      2. 7.3.2  Power Stage
      3. 7.3.3  Input and Output Capacitors
      4. 7.3.4  Oscillator And Watchdog Circuit
      5. 7.3.5  Synchronization
      6. 7.3.6  SWOUT
      7. 7.3.7  Soft Start
      8. 7.3.8  Load Regulation
      9. 7.3.9  Thermal Performance
        1. 7.3.9.1 Thermal Protection
      10. 7.3.10 Current Limit
      11. 7.3.11 Construction
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Ripple Reduction
      2. 8.1.2 Connecting the DCPA1 in Series
      3. 8.1.3 Connecting the DCPA1 in Parallel
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 DCPA10505 Application Curves
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor
        2. 8.2.3.2 Output Capacitor
        3. 8.2.3.3 SYNCIN Pin
      4. 8.2.4 PCB Design
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 関連リンク
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Due to the high power density of these devices, provide ground planes on the input and output rails.

Figure 40 shows the schematic for a single output DCPA1 device. Figure 40 illustrates a printed circuit board (PCB) layout for the schematics.

Including input power and ground planes provides a low-impedance path for the input power. For the output, the COM signal connects via a ground plane, while the connections for the positive and negative voltage outputs conduct via wide traces in order to minimize losses.

The output should be taken from the device using ground and power planes, thereby ensuring minimum losses.

The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.

If the SYNCIN pin is unused, it is recommended to connect this pin to the input side common, –VS. Allow the SWOUT pin, to remain configured as a floating pad.

10.2 Layout Example

DCPA10505 DCPA10505D DCPA10512 DCPA10512D DCPA10515 DCPA10515D DSSingleTop2.gif Figure 40. Typical Layout