JAJSMN8D December   2000  – August 2021 DCR021205 , DCR022405

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Isolation
        1. 7.3.1.1 Operation or Functional Isolation
        2. 7.3.1.2 Basic or Enhanced Isolation
        3. 7.3.1.3 Working Voltage
        4. 7.3.1.4 Isolation Voltage Rating
        5. 7.3.1.5 Repeated High-Voltage Isolation Testing
      2. 7.3.2 Power Stage
      3. 7.3.3 Oscillator and Watchdog
      4. 7.3.4 ERROR Flag
      5. 7.3.5 Synchronization
      6. 7.3.6 Construction
      7. 7.3.7 Decoupling – Ripple Reduction
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Disable and Enable
      2. 7.4.2 Regulated Output Disable and Enable
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DCR02 Single Voltage Output
      2. 8.1.2 Generating Two Positive Output Voltages
      3. 8.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR02s
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Filter Capacitor
        4. 8.2.2.4 ERROR Flag
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Consideration
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

At TA = +25°C, VS = nominal, IOUT = 10 mA, COUT = 0.1-µF ceramic, and CIN = 2.2-µF ceramic, unless otherwise noted.(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OUTPUT
Nominal output voltage (+VOUT)5V
Setpoint accuracy0.5%2%
Maximum output current400mA
Output short-circuit protectedDurationInfinite
Line regulation1mV/V
Over line and load10-mA to 400-mA load, over +VS range1%2.5%
Temperature variation–40°C to 70°C1%
Ripple and noiseDCR0212 ripple, 20−MHz bandwidth, 50% load(1)18mVPP
DCR0212 noise, 100−MHz bandwidth, 50% load(1)20
DCR0224 ripple, 20−MHz bandwidth, 50% load(1)18
DCR0224 noise, 100−MHz bandwidth, 50% load(1)25
INPUT
Nominal voltage (+VS)DCR02240512V
DCR02120524
Voltage range–10%10%
Supply currentDCR021205IO = 0 mA15mA
IO = 10 mA23
IO = 400 mA250
DCR022405IO = 0 mA15
IO = 10 mA17
IO = 400 mA129
Reflected ripple current20−MHz bandwidth, 100% load(1)8mAPP
ISOLATION
Voltage1-s flash testVoltage1kVrms
dV/dt500V/s
Leakage current30nA
Continuous working voltage across isolation barrierDC60VDC
AC42.5VAC
Barrier capacitance25pF
OUTPUT ENABLE CONTROL
Logic high input voltage2VRECV
Logic high input current2 < VENABLE < VREG100nA
Logic low input voltage–0.20.5V
Logic low input current0 < VENABLE < 0.5100nA
ERROR FLAG
Logic high open collector leakageVERROR = 5 V10µA
Logic low output voltageSinking 2 mA0.4V
THERMAL SHUTDOWN
Junction temperatureTemp activated150°C
Temp deactivated130
SYNCHRONIZATION PIN
Internal oscillator frequency720800880kHz
External synchronization frequency720880kHz
External synchronization signal high2.53V
External synchronization signal low00.4V
External capacitance on SYNC pin3pF
(1) Ceramic capacitors, CIN = 2.2 µF, CFILTER = 1 µF, and COUT = 0.1 µF.