JAJSMN8D
December 2000 – August 2021
DCR021205
,
DCR022405
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Isolation
7.3.1.1
Operation or Functional Isolation
7.3.1.2
Basic or Enhanced Isolation
7.3.1.3
Working Voltage
7.3.1.4
Isolation Voltage Rating
7.3.1.5
Repeated High-Voltage Isolation Testing
7.3.2
Power Stage
7.3.3
Oscillator and Watchdog
7.3.4
ERROR Flag
7.3.5
Synchronization
7.3.6
Construction
7.3.7
Decoupling – Ripple Reduction
7.4
Device Functional Modes
7.4.1
Device Disable and Enable
7.4.2
Regulated Output Disable and Enable
8
Application and Implementation
8.1
Application Information
8.1.1
DCR02 Single Voltage Output
8.1.2
Generating Two Positive Output Voltages
8.1.3
Generation of Dual Polarity Voltages from Two Self-Synchronized DCR02s
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input Capacitor
8.2.2.2
Output Capacitor
8.2.2.3
Filter Capacitor
8.2.2.4
ERROR Flag
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
10.3
Thermal Consideration
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DVS|10
MPDS113
NVE|10
MPDI055
サーマルパッド・メカニカル・データ
発注情報
jajsmn8d_oa
jajsmn8d_pm
10.2
Layout Examples
Figure 10-1
PCB Layout Example, Component-Side View
Figure 10-3
DCR02 PCB Schematic, U Package
Figure 10-2
PCB Layout Example, Non-Component-Side View