JAJSVE5 September   2024 DDS39RF12 , DDS39RFS12

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.2 Using the Fast Reconfiguration Interface

The FR interface provides fast write-only access to configure NCO frequencies and synchronization. The FR interface is similar to the SPI interface, but 4 bits are sent per clock cycle. The FR timing diagram is shown in Figure 7-60. It uses a R/W bit (always Write for this device), a transaction sync bit (FRS), and 14-bits of address followed by some number of data bytes. The address is decremented after each data byte (consistent with little-endian). The interface is byte addressable and data is committed after each byte. The FR interface is takes 4-bits (one nibble) per clock. For multi-nibble fields, data is sent most-significant nibble first. When the transaction sync bit (FRS) is set, the synchronization event specified in the NCO_SYNC_SRC register field occurs at the rising edge of FRCS. Transactions ended before the completion of the first data byte may not trigger the sync event.

DDS39RF12 DDS39RFS12 FR Interface Timing DiagramFigure 7-60 FR Interface Timing Diagram

The FR interface registers are listed in Table 7-31. There are two registers that can change the NCO frequency - FR_FREQL[3:0] is 64-bits for each NCO and changes the entire frequency word. FR_FREQS[3:0] is 32-bits for each NCO and changes only the upper 32-bits of the frequency word, providing for faster frequency changes.

Table 7-31 FR Interface Registers
AddressNameDescription
0x00FFFR_NCO_AR

FR NCO Accumulator Reset (default: 0x0f)

[7:4] RESERVED

[3:0] FR_NCO_AR For each bit FR_NCO_AR[n], if set, the accumulator for NCOn is reset on every sync event specified by NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=0.

0x0100-0x011FFR_FREQL[3:0]

FR 64-bit Frequency for NCO Accumulator (default for FR_FREQL[n]=0x00)

The frequency setting for FR_FREQL[0] is at the lowest address.

[63:0] FR_FREQL[n] This register is used instead of FREQ[n] when FR_EN=1. Changes to the upper 32-bits of this register also change FR_FREQS[n].

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=0.

0x0120-0x0127FR_PHASE[3:0]

FR Phase for NCO Accumulator (default for FR_PHASE[n]=0x0000)

The phase setting for FR_PHASE[0] is at the lowest address.

[15:0] FR_PHASE[n] This register is used instead of PHASE[n] when FR_EN=1.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=0.

0x0128-0x0137FR_FREQS[3:0]

FR 32-bit Frequency for NCO Accumulator (default for FR_FREQS[n]=0x00)

The frequency setting for FR_FREQS[0] is at the lowest address.

[31:0] FR_FREQS[n] This register is used instead of FREQ[n] when FR_EN=1. Changes to this register also change the upper 32-bits of FR_FREQL[n]. This register only controls the upper 32-bits of the frequency. The lower 32-bits of the frequency are always controlled by FR_FREQL[n].

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=0.