JAJSVE5 September   2024 DDS39RF12 , DDS39RFS12

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2.1 JESD204C Interface Modes

The device JESD204C modes are configured with the parameters defined in Table 7-19, Table 7-20 and Table 7-21.

Table 7-19 JESD204C Interface Parameter Definitions
ParameterDescription
JMODEJESD204C mode number. The user configures this parameter to choose a supported mode. Most other parameters are derived from this setting. See Table 7-22.
LSLanes per sample stream. This is derived from JMODE. See Table 7-22.
LTRatio of clock to input sample rate. LT = FCLK / FINPUT. Not that DES2X mode does not affect the value of LT.

Interpolation factor 1-256x is programmed in the DUC_L register.

LxMaximum number of lanes used for a given JMODE. The link scales down the number of active lanes (L) depending on how many channels are enabled. See JESD_M register.
MxMaximum number of streams for a given JMODE. Mx is computed automatically according to Table 7-22. The user can specify the actual number of streams (M) using the JESD_M register.
RNumber of bits transmitted per lane per CLK cycle. Derived from JMODE and LT (see )Table 7-22. Based on R, the user must program REFDIV, MPY, and RATE registers. Additionally, the maximum CLK frequency is a function of R.
SISample Interleaving/Increment Factor. A value of 1 indicates that the standard transport layer mapping from the JESD204C standard is used (samples are mapped linearly from 0 to S-1). A value greater than 1 indicates that an alternate mapping is used as follows: Map samples starting with sample 0, incrementing the index by SI. Repeat this as many times as necessary to map all S samples, starting each repetition at an index that is one larger than the previous repetition. See JESD Format Diagrams JESD Format Diagrams.
KRFor 8b/10b operation, KR defines the legal values of K (frames per multiframe). The legal values are restricted to facilitate upset immunity of the elastic buffer. The multiframe length is restricted to a multiple of the elastic buffer depth of 64 characters (buffer depth is reduced to 32 characters if K=32 and F=1). For 8b/10b modes, K is programmed via the KM1 register.
Table 7-20 JESD204C Link Parameters
ParameterDescriptionILAS Field NameValue for this device(1)
ADJCNTDAC LMFC adjustmentADJCNT[3:0]n/a
ADJDIRDAC LMFC adjustment directionADJDIR[0]n/a
BIDBank IDBID[3:0]n/a
CFNumber of control words per frameCF[4:0]0
CSNumber. of control bits per sampleCS[1:0]0
DIDDevice identification numberDID[7:0]n/a
FNumber of octets per frame (per lane)F[7:0]See Table 7-22
HDHigh Density FormatHD[0]See Table 7-22
JESDVJESD204 VersionJESDV[2:0]n/a
KNumber of frames per multiframeK[7:0]Set by KM1register
LNumber of lanes per linkL[4:0]ceiling(M/Mx*Lx)
LIDLane identification no.LID[4:0]n/a
MNumber of sample streams per link (see (1))M[7:0]Set by JESD_M register
NBits per sample (before adding control or tail bits) for JESD204C interface.N[4:0]See Table 7-22
N'Total number of bits per sample (including control and tail bits) for JESD204C interface.N’[4:0]See Table 7-22
PHADJPhase adjustment request to DACPHADJ[0]n/a
SNumber of samples per stream per frameS[4:0]See Table 7-22
SCRScrambling enabledSCR[0]Set by SCR register
SUBCLASSVDevice Subclass VersionSUBCLASSV[2:0]n/a
RES1Reserved field 1RES1[7:0]n/a
RES2Reserved field 2RES2[7:0]n/a
CHKSUMChecksum (sum of all above fields, modulo 256)FCHK[7:0]n/a
(1) In 8b/10b modes, the transmitter may send link configuration octets during the ILAS. The values sent by the transmitter are not checked by this receiver, and they do not need to match the operational values of the receiver.
Table 7-21 Link Parameters (applicable in 64b/66b encoding only)
ParameterDescriptionValue for this device(1)
ENumber of multi-blocks per extended multi-block (64b/66b encoding only)1

Each supported mode is assigned a mode number which can be programmed into the JMODE register with the parameters listed in Table 7-22.

  1. At minimum interpolation rate
Table 7-22 JESD Interface Modes
JMODE Encoding Max Input Sample Rate per Stream (MSPS)#GUID-6D01121F-27FF-4679-9595-503775437EB9 MAX Serdes Baud Rate (Gbps) R =

FBIT/ FCLK

 N Mx = Max # Streams Ls = Lanes/Stream Lx = Max # Lanes LT = Interpolation JESD Format KR
MIN MAX F S HD SI
4 8b/10b 640 12.8 20/LT 16 2 1 2 4 64 2 1 0 1 32, 64, 128
64b/66b 775.8 12.8 16.5/LT
5 8b/10b 320 12.8 40/LT 16 4 ½ 2 8 128 4 1 0 1 16,32,64
64b/66b 387.9 12.8 33/LT
6 8b/10b 160 12.8 80/LT 16 8 ¼ 2 16 256 8 1 0 1 8,16,32
64b/66b 193.9 12.8 66/LT
7 8b/10b 80 12.8 160/LT 16 8 ⅛ 1 32 256 16 1 0 1 4,8,16
64b/66b 97.0 12.8 132/LT