JAJSGY9 データシート

JAJSGY9C february 2019 – july 2023 DLP2010

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FQJ|40
- MCLG028B

サーマルパッド・メカニカル・データ

発注情報

jajsgy9c_oa

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS⁽²⁾	MIN	TYP	MAX	UNIT
CURRENT
I_DD	Supply current: VDD⁽³⁾⁽⁴⁾	VDD = 1.95 V			34.7	mA
I_DD	Supply current: VDD⁽³⁾⁽⁴⁾	VDD = 1.8 V		27.5		mA
I_DDI	Supply current: VDDI⁽³⁾⁽⁴⁾	VDDI = 1.95 V			9.4	mA
I_DDI	Supply current: VDDI⁽³⁾⁽⁴⁾	VDD = 1.8 V		6.6		mA
I_OFFSET	Supply current: VOFFSET⁽⁵⁾⁽⁶⁾	VOFFSET = 10.5 V			1.7	mA
I_OFFSET	Supply current: VOFFSET⁽⁵⁾⁽⁶⁾	VOFFSET = 10 V		0.9		mA
I_BIAS	Supply current: VBIAS⁽⁵⁾⁽⁶⁾	VBIAS = 18.5 V			0.4	mA
I_BIAS	Supply current: VBIAS⁽⁵⁾⁽⁶⁾	VBIAS = 18 V		0.2		mA
I_RESET	Supply current: VRESET⁽⁶⁾	VRESET = –14.5 V			2	mA
I_RESET	Supply current: VRESET⁽⁶⁾	VRESET = –14 V		1.2		mA
POWER⁽⁷⁾
P_DD	Supply power dissipation: VDD⁽³⁾⁽⁴⁾	VDD = 1.95 V			67.7	mW
P_DD	Supply power dissipation: VDD⁽³⁾⁽⁴⁾	VDD = 1.8 V		49.5		mW
P_DDI	Supply power dissipation: VDDI⁽³⁾⁽⁴⁾	VDDI = 1.95 V			18.3	mW
P_DDI	Supply power dissipation: VDDI⁽³⁾⁽⁴⁾	VDD = 1.8 V		11.9		mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁵⁾⁽⁶⁾	VOFFSET = 10.5 V			17.9	mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁵⁾⁽⁶⁾	VOFFSET = 10 V		9		mW
P_BIAS	Supply power dissipation: VBIAS⁽⁵⁾⁽⁶⁾	VBIAS = 18.5 V			7.4	mW
P_BIAS	Supply power dissipation: VBIAS⁽⁵⁾⁽⁶⁾	VBIAS = 18 V		3.6		mW
P_RESET	Supply power dissipation: VRESET⁽⁶⁾	VRESET = –14.5 V			29	mW
P_RESET	Supply power dissipation: VRESET⁽⁶⁾	VRESET = –14 V		16.8		mW
P_TOTAL	Supply power dissipation: Total			90.8	140.3	mW
LPSDR INPUT⁽⁸⁾
V_IH(DC)	DC input high voltage⁽⁹⁾		0.7 × VDD		VDD + 0.3	V
V_IL(DC)	DC input low voltage⁽⁹⁾		–0.3		0.3 × VDD	V
V_IH(AC)	AC input high voltage⁽⁹⁾		0.8 × VDD		VDD + 0.3	V
V_IL(AC)	AC input low voltage⁽⁹⁾		–0.3		0.2 × VDD	V
∆V_T	Hysteresis ( V_T+ – V_T– )	Figure 6-11	0.1 × VDD		0.4 × VDD	V
I_IL	Low–level input current	VDD = 1.95 V; V_I = 0 V	–100			nA
I_IH	High–level input current	VDD = 1.95 V; V_I = 1.95 V			100	nA
LPSDR OUTPUT⁽¹⁰⁾
V_OH	DC output high voltage	I_OH = –2 mA	0.8 × VDD			V
V_OL	DC output low voltage	I_OL = 2 mA			0.2 × VDD	V
CAPACITANCE
C_IN	Input capacitance LPSDR	ƒ = 1 MHz			10	pF
C_IN	Input capacitance SubLVDS	ƒ = 1 MHz			20	pF
C_OUT	Output capacitance	ƒ = 1 MHz			10	pF
C_RESET	Reset group capacitance	ƒ = 1 MHz; (480 × 108) micromirrors	95		113	pF

(1) Device electrical characteristics are over Section 6.4 unless otherwise noted.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.