JAJSJ81 データシート

JAJSJ81C may 2020 – july 2023 DLP2010LC

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FQJ|40
- MCLG028B

サーマルパッド・メカニカル・データ

発注情報

6.1 Absolute Maximum Ratings

See ⁽¹⁾

			MIN	MAX	UBIT
Supply voltage	VDD	for LVCMOS core logic⁽²⁾ Supply voltage for LPSDR low speed interface	–0.5	2.3	V
	VDDI	for SubLVDS receivers⁽²⁾	–0.5	2.3
	VOFFSET	for HVCMOS and micromirror electrode⁽²⁾⁽³⁾	–0.5	10.6
	VBIAS	for micromirror electrode⁽²⁾	–0.5	19
	VRESET	for micromirror electrode⁽²⁾	–15	0.5
	\| VDDI–VDD \|	delta (absolute value)⁽⁴⁾		0.3
	\| VBIAS–VOFFSET \|	delta (absolute value)⁽⁵⁾		11
	\| VBIAS–VRESET \|	delta (absolute value)⁽⁶⁾		34
Input voltage	for other inputs LPSDR⁽²⁾		–0.5	VDD + 0.5	V
Input voltage	for other inputs SubLVDS⁽²⁾⁽⁷⁾		–0.5	VDDI + 0.5	V
Input pins	\| VID \|	SubLVDS input differential voltage (absolute value)⁽⁷⁾		810	mV
Input pins	IID	SubLVDS input differential current		8.1	mA
Clock frequency	ƒ_clock	Clock frequency for low speed interface LS_CLK		130	MHz
Clock frequency	ƒ_clock	Clock frequency for high speed interface DCLK		620	MHz
Environmental	T_ARRAY and T_WINDOW	Temperature – operational⁽⁸⁾	–20	90	°C
	T_ARRAY and T_WINDOW	Temperature – non-operational⁽⁸⁾	–40	90
	T_DP	Dew Point Temperature - operating and non-operating (non-condensing)		81
	\|T_DELTA\|	Absolute Temperature delta between any point on the window edge and the ceramic test point TP1⁽⁹⁾		30

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated by the Section 7.6), or of any point along the Window Edge as defined in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.