JAJSFS0G July   2018  – October 2024 DLP230NP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 ディスプレイ アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Switching Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 Chipset Resources
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MIN NOM MAX UNIT
LPSDR
tr Rise slew rate(1) (30% to 80%) × VDD, Figure 5-3 1 3 V/ns
tƒ Fall slew rate(1) (70% to 20%) × VDD, Figure 5-3 1 3 V/ns
tr Rise slew rate(2) (20% to 80%) × VDD, Figure 5-3 0.25 V/ns
tƒ Fall slew rate(2) (80% to 20%) × VDD, Figure 5-3 0.25 V/ns
tc Cycle time LS_CLK Figure 5-2 7.7 8.3 ns
tW(H) Pulse duration LS_CLK high 50% to 50% reference points, Figure 5-2 3.1 ns
tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 5-2 3.1 ns
tsu Setup time LS_WDATA valid before LS_CLK ↑, Figure 5-2 1.5 ns
th Hold time LS_WDATA valid after LS_CLK ↑, Figure 5-2 1.5 ns
tWINDOW Window time(1) (3) Setup time + hold time, Figure 5-2 3 ns
tDERATING Window time derating(1) (3) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 5-5 0.35 ns
SubLVDS
tr Rise slew rate 20% to 80% reference points, Figure 5-4 0.7 1 V/ns
tƒ Fall slew rate 80% to 20% reference points, Figure 5-4 0.7 1 V/ns
tc Cycle time DCLK Figure 5-6 1.79 1.85 ns
tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 5-6 0.79 ns
tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 5-6 0.79 ns
tsu Setup time D(0:7) valid before
DCLK ↑ or DCLK ↓, Figure 5-6
th Hold time D(0:7) valid after
DCLK ↑ or DCLK ↓, Figure 5-6
tWINDOW Window time Setup time + hold time, Figure 5-6, Figure 5-7 0.3 ns
tLVDS-ENABLE+REFGEN Power-up receiver(4) 2000 ns
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 5-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 5-3.
(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
DLP230NP LPSDR Switching Parameters
Low-speed interface is LPSDR and adheres to Section 5.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
Figure 5-2 LPSDR Switching Parameters
DLP230NP LPSDR Input Rise and Fall Slew RateFigure 5-3 LPSDR Input Rise and Fall Slew Rate
DLP230NP SubLVDS Input Rise and Fall Slew RateFigure 5-4 SubLVDS Input Rise and Fall Slew Rate
DLP230NP Window Time Derating ConceptFigure 5-5 Window Time Derating Concept
DLP230NP SubLVDS Switching ParametersFigure 5-6 SubLVDS Switching Parameters
DLP230NP High-Speed Training Scan Window
Note: Refer to Section 6.3.3 for details.
Figure 5-7 High-Speed Training Scan Window
DLP230NP SubLVDS Voltage ParametersFigure 5-8 SubLVDS Voltage Parameters
DLP230NP SubLVDS Waveform ParametersFigure 5-9 SubLVDS Waveform Parameters
DLP230NP SubLVDS Equivalent Input CircuitFigure 5-10 SubLVDS Equivalent Input Circuit
DLP230NP LPSDR Input HysteresisFigure 5-11 LPSDR Input Hysteresis
DLP230NP LPSDR Read OutFigure 5-12 LPSDR Read Out
DLP230NP Test Load Circuit for Output Propagation Measurement
See Section 6.3.4 for more information.
Figure 5-13 Test Load Circuit for Output Propagation Measurement