JAJSJ75 データシート

JAJSJ75C april 2020 – july 2023 DLP3010LC

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FQK|57
- MCLG029B

サーマルパッド・メカニカル・データ

発注情報

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁰⁾

PARAMETER		TEST CONDITIONS⁽²⁾	MIN	TYP	MAX	UNIT
CURRENT
I_DD	Supply current: VDD⁽³⁾⁽⁵⁾	VDD = 1.95 V			60.5	mA
I_DD	Supply current: VDD⁽³⁾⁽⁵⁾	VDD = 1.8 V		54		mA
I_DDI	Supply current: VDDI⁽³⁾⁽⁵⁾	VDDI = 1.95 V			16.5	mA
I_DDI	Supply current: VDDI⁽³⁾⁽⁵⁾	VDD = 1.8 V		11.3		mA
I_OFFSET	Supply current: VOFFSET⁽⁴⁾⁽⁶⁾	VOFFSET = 10.5 V			2.2	mA
I_OFFSET	Supply current: VOFFSET⁽⁴⁾⁽⁶⁾	VOFFSET = 10 V		1.5		mA
I_BIAS	Supply current: VBIAS⁽⁴⁾⁽⁶⁾	VBIAS = 18.5 V			0.6	mA
I_BIAS	Supply current: VBIAS⁽⁴⁾⁽⁶⁾	VBIAS = 18 V		0.3		mA
I_RESET	Supply current: VRESET⁽⁶⁾	VRESET = –14.5 V			2.4	mA
I_RESET	Supply current: VRESET⁽⁶⁾	VRESET = –14 V		1.7		mA
POWER⁽¹⁾
P_DD	Supply power dissipation: VDD⁽³⁾⁽⁵⁾	VDD = 1.95 V			118	mW
P_DD	Supply power dissipation: VDD⁽³⁾⁽⁵⁾	VDD = 1.8 V		97.2		mW
P_DDI	Supply power dissipation: VDDI⁽³⁾⁽⁵⁾	VDDI = 1.95 V			32	mW
P_DDI	Supply power dissipation: VDDI⁽³⁾⁽⁵⁾	VDD = 1.8 V		20		mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁴⁾⁽⁶⁾	VOFFSET = 10.5 V			23	mW
P_OFFSET	Supply power dissipation: VOFFSET⁽⁴⁾⁽⁶⁾	VOFFSET = 10 V		15		mW
P_BIAS	Supply power dissipation: VBIAS⁽⁴⁾⁽⁶⁾	VBIAS = 18.5 V			11	mW
P_BIAS	Supply power dissipation: VBIAS⁽⁴⁾⁽⁶⁾	VBIAS = 18 V		6		mW
P_RESET	Supply power dissipation: VRESET⁽⁶⁾	VRESET = –14.5 V			35	mW
P_RESET	Supply power dissipation: VRESET⁽⁶⁾	VRESET = –14 V		24		mW
P_TOTAL	Supply power dissipation: Total			162.2	219	mW
LPSDR INPUT⁽⁷⁾
V_IH(DC)	DC input high voltage⁽⁹⁾		0.7 × VDD		VDD + 0.3	V
V_IL(DC)	DC input low voltage⁽⁹⁾		–0.3		0.3 × VDD	V
V_IH(AC)	AC input high voltage⁽⁹⁾		0.8 × VDD		VDD + 0.3	V
V_IL(AC)	AC input low voltage⁽⁹⁾		–0.3		0.2 × VDD	V
∆V_T	Hysteresis ( V_T+ – V_T– )	Figure 6-12	0.1 × VDD		0.4 × VDD	V
I_IL	Low–level input current	VDD = 1.95 V; V_I = 0 V	–100			nA
I_IH	High–level input current	VDD = 1.95 V; V_I = 1.95 V			100	nA
LPSDR OUTPUT⁽⁸⁾
V_OH	DC output high voltage	I_OH = –2 mA	0.8 × VDD			V
V_OL	DC output low voltage	I_OL = 2 mA			0.2 × VDD	V
CAPACITANCE
C_IN	Input capacitance LPSDR	ƒ = 1 MHz			10	pF
C_IN	Input capacitance SubLVDS	ƒ = 1 MHz			10	pF
C_OUT	Output capacitance	ƒ = 1 MHz			10	pF
C_RESET	Reset group capacitance	ƒ = 1 MHz; (720 × 160) micromirrors	200		220	pF

(1) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(5) Supply power dissipation based on non–compressed commands and data.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(8) LPSDR specification is for pin LS_RDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) Device electrical characteristics are over Section 6.4 unless otherwise noted.