JAJSJ75C april 2020 – july 2023 DLP3010LC
PRODUCTION DATA
PIN | TYPE | SIGNAL | DATA RATE | DESCRIPTION | PACKAGE NET LENGTH(2) (mm) | |
---|---|---|---|---|---|---|
NAME | NO. | |||||
DATA INPUTS | ||||||
D_N(0) | C9 | I | SubLVDS | Double | Data, Negative | 10.54 |
D_P(0) | B9 | I | SubLVDS | Double | Data, Positive | 10.54 |
D_N(1) | D10 | I | SubLVDS | Double | Data, Negative | 13.14 |
D_P(1) | D11 | I | SubLVDS | Double | Data, Positive | 13.14 |
D_N(2) | C11 | I | SubLVDS | Double | Data, Negative | 14.24 |
D_P(2) | B11 | I | SubLVDS | Double | Data, Positive | 14.24 |
D_N(3) | D12 | I | SubLVDS | Double | Data, Negative | 14.35 |
D_P(3) | D13 | I | SubLVDS | Double | Data, Positive | 14.35 |
D_N(4) | D4 | I | SubLVDS | Double | Data, Negative | 5.89 |
D_P(4) | D5 | I | SubLVDS | Double | Data, Positive | 5.89 |
D_N(5) | C5 | I | SubLVDS | Double | Data, Negative | 5.45 |
D_P(5) | B5 | I | SubLVDS | Double | Data, Positive | 5.45 |
D_N(6) | D6 | I | SubLVDS | Double | Data, Negative | 8.59 |
D_P(6) | D7 | I | SubLVDS | Double | Data, Positive | 8.59 |
D_N(7) | C7 | I | SubLVDS | Double | Data, Negative | 7.69 |
D_P(7) | B7 | I | SubLVDS | Double | Data, Positive | 7.69 |
DCLK_N | D8 | I | SubLVDS | Double | Clock, Negative | 8.10 |
DCLK_P | D9 | I | SubLVDS | Double | Clock, Positive | 8.10 |
CONTROL INPUTS | ||||||
LS_WDATA | C12 | I | LPSDR(1) | Single | Write data for low speed interface. | 7.16 |
LS_CLK | C13 | I | LPSDR | Single | Clock for low-speed interface | 7.89 |
DMD_DEN_ARSTZ | C14 | I | LPSDR | Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. | ||
LS_RDATA | C15 | O | LPSDR | Single | Read data for low-speed interface | |
POWER(3) | ||||||
VBIAS | C1 | Power | Supply voltage for positive bias level at micromirrors | |||
VBIAS | C18 | Power | ||||
VOFFSET | D1 | Power | Supply
voltage for HVCMOS core logic. Supply voltage for stepped high level
at micromirror address electrodes. Supply voltage for offset level at micromirrors. |
|||
VOFFSET | D17 | Power | ||||
VRESET | B1 | Power | Supply voltage for negative reset level at micromirrors. | |||
VRESET | B18 | Power | ||||
VDD | B6 | Power | ||||
VDD | B10 | Power | ||||
VDD | B19 | Power | ||||
VDD | C6 | Power | Supply voltage for LVCMOS core logic. Supply voltage for LPSDR
inputs. Supply voltage for normal high level at micromirror address electrodes. |
|||
VDD | C10 | Power | ||||
VDD | C19 | Power | ||||
VDD | D2 | Power | ||||
VDD | D18 | Power | ||||
VDD | D19 | Power | ||||
VDDI | B2 | Power | Supply voltage for SubLVDS receivers. | |||
VDDI | C2 | Power | ||||
VDDI | C3 | Power | ||||
VDDI | D3 | Power | ||||
VSS | B3 | Ground | Common return. Ground for all power. |
|||
VSS | B4 | Ground | ||||
VSS | B8 | Ground | ||||
VSS | B12 | Ground | ||||
VSS | B13 | Ground | ||||
VSS | B14 | Ground | ||||
VSS | B15 | Ground | ||||
VSS | B16 | Ground | ||||
VSS | B17 | Ground | ||||
VSS | C4 | Ground | ||||
VSS | C8 | Ground | ||||
VSS | C16 | Ground | ||||
VSS | C17 | Ground | ||||
VSS | D14 | Ground | ||||
VSS | D15 | Ground | ||||
VSS | D16 | Ground |
NUMBER | SYSTEM BOARD | ||
---|---|---|---|
A13 | Do not connect | ||
A14 | Do not connect | ||
A15 | Do not connect | ||
A16 | Do not connect | ||
A17 | Do not connect | ||
A18 | Do not connect | ||
E13 | Do not connect | ||
E14 | Do not connect | ||
E15 | Do not connect | ||
E16 | Do not connect | ||
E17 | Do not connect | ||
E18 | Do not connect |