JAJSNF8 February   2022 DLP3020-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 DMD JTAG Interface
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Device Handling
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1 Power Supply Sequencing Requirements

  • VBIAS, VCC, VOFFSET, VREF, VRESET, VSS are required to operate the DMD.
CAUTION:
  • For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power up and power down procedures may affect device reliability.
  • The VCC, VREF, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power up and power down operations. Failure to meet any of the following requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 9-1. VSS must also be connected.

DMD Power Supply Power Up Procedure:

  • During power up, VCC and VREF must always start and settle before VOFFSET, VBIAS and VRESET voltages are applied to the DMD.
  • During power up, VBIAS does not have to start after VOFFSET. However, it is a strict requirement that the delta between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for Figure 9-1).
  • During power up, the DMD’s LVCMOS input pins shall not be driven high until after VCC and VREF have settled at operating voltage.
  • During power up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates during power up are flexible, provided that the transient voltage levels follow the requirements listed previously in Section 6.4 and in Figure 9-1.

DMD Power Supply Power Down Procedure

  • VCC and VREF must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
  • During power down it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that the delta between VBIAS and VOFFSET must be within ±8.75 V (refer to Note 1 for Figure 9-1).
  • During power down, the DMD’s LVCMOS input pins must be less than VREF + 0.3 V.
  • During power down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates during power down are flexible, provided that the transient voltage levels follow the requirements listed previously in Section 6.4 and in Figure 9-1.