JAJSNF8
February 2022
DLP3020-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
説明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Storage Conditions
6.3
ESD Ratings
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Timing Requirements
6.8
Switching Characteristics
6.9
System Mounting Interface Loads
6.10
Physical Characteristics of the Micromirror Array
6.11
Micromirror Array Optical Characteristics
6.12
Window Characteristics
6.13
Chipset Component Usage Specification
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Micromirror Array
7.3.2
Double Data Rate (DDR) Interface
7.3.3
Micromirror Switching Control
7.3.4
DMD Voltage Supplies
7.3.5
Logic Reset
7.3.6
Temperature Sensing Diode
7.3.6.1
Temperature Sense Diode Theory
7.3.7
DMD JTAG Interface
7.4
System Optical Considerations
7.4.1
Numerical Aperture and Stray Light Control
7.4.2
Pupil Match
7.4.3
Illumination Overfill and Alignment
7.5
DMD Image Performance Specification
7.6
Micromirror Array Temperature Calculation
7.7
Micromirror Landed-On/Landed-Off Duty Cycle
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.3
Application Mission Profile Consideration
9
Power Supply Recommendations
9.1
Power Supply Sequencing Requirements
9.1.1
Power Up and Power Down
10
Layout
10.1
Layout Guidelines
10.2
Temperature Diode Pins
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.1.2
Device Markings
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
サポート・リソース
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Device Handling
11.8
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
FQR|54
MCCC009
サーマルパッド・メカニカル・データ
発注情報
jajsnf8_oa
6.8
Switching Characteristics
Over operating free-air temperature range (unless otherwise noted).
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
PD
Output propagation, clock to Q (see
Figure 6-4
)
C
L
= 11 pF, from (Input) falling edge of TCK to (Output) TDO, see
Figure 6-4
3
25
ns
(1)
Device electrical characteristics are over
Recommended Operating Characteristics
unless otherwise noted.
Figure 6-5
Test Load Circuit for Output Propagation Measurement