JAJSI71C April   2019  – February 2023 DLP470NE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1)
VOH High level output voltage VCC = 1.8 V, IOH = –2 mA 0.8 × VCC V
VOL Low level output voltage VCC = 1.95 V, IOL = 2 mA 0.2 × VCC V
IOZ High impedance output current VCC = 1.95 V –40 25 µA
IIL Low level input current VCC = 1.95 V, VI = 0 –1 µA
IIH High level input current(2)(3) VCC = 1.95 V, VI = VCC 110 µA
ICC Supply current VCC VCC = 1.95 V 715 mA
IOFFSET Supply current VOFFSET(3) VOFFSET = 10.5 V 7 mA
IBIAS Supply current VBIAS(3) (4) VBIAS = 18.5 V 2.75 mA
IRESET Supply current VRESET(4) VRESET = –14.5 V -5 mA
PCC Supply power dissipation VCC VCC = 1.95 V 1394.25 mW
POFFSET Supply power dissipation VOFFSET(3) VOFFSET = 10.5 V 73.50 mW
PBIAS Supply power dissipation VBIAS(3)(4) VBIAS = 18.5 V 50.87 mW
PRESET Supply power dissipation VRESET(4) VRESET = –14.5 V 72.5 mW
PTOTAL Supply power dissipation VTOTAL 1591.12 mW
(1) All voltage values are with respect to the ground pins (VSS).
(2) Applies to LVCMOS pins only. Excludes LVDS pins and MBRST (15:0) pins.
(3) To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limits listed in the Recommended Operating Conditions table.
(4) To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit in Recommended Operating Conditions.