JAJSOE9B april   2019  – march 2023 DLP470TE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
      1. 6.8.1 Timing Diagrams
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 サード・パーティ製品に関する免責事項
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
      2. 11.3.2 サポート・リソース
      3. 11.3.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under Section 6.1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device reliability.

MIN MAX UNIT
SUPPLY VOLTAGES
VCC Supply voltage for LVCMOS core logic(1) –0.5 2.3 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(1)(2) –0.5 11 V
VBIAS Supply voltage for micromirror electrode(1) –0.5 19 V
VRESET Supply voltage for micromirror electrode(1) –15 –0.3 V
|VBIAS – VOFFSET| Supply voltage difference (absolute value)(3) 11 V
|VBIAS – VRESET| Supply voltage difference (absolute value)(4) 34 V
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins(1) –0.5 VCC + 0.5 V
Input voltage for all other LVDS input pins (1)(5) –0.5 VCC + 0.5 V
|VID| Input differential voltage (absolute value)(6) 500 mV
IID Input differential current(5) 6.3 mA
Clocks
ƒCLOCK Clock frequency for LVDS interface, DCLK_A 400 MHz
ƒCLOCK Clock frequency for LVDS interface, DCLK_B 400 MHz
ƒCLOCK Clock frequency for LVDS interface, DCLK_C 400 MHz
ƒCLOCK Clock frequency for LVDS interface, DCLK_D 400 MHz
ENVIRONMENTAL
TARRAY and TWINDOW Temperature, operating(7) 0 90 °C
Temperature, non–operating(7) –40 90 °C
|TDELTA| Absolute temperature delta between any point on the window edge and the ceramic test point TP1 (8) 30 °C
TDP Dew point temperature, operating and non–operating (non-condensing) 81 °C
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(4) Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
(5) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the window edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, use that location.
(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, use that location.