JAJSOE9B april   2019  – march 2023 DLP470TE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
      1. 6.8.1 Timing Diagrams
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 サード・パーティ製品に関する免責事項
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
      2. 11.3.2 サポート・リソース
      3. 11.3.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Timing Requirements

MIN NOM MAX UNIT
SCP(1)
tr Rise time 20% to 80% reference points 30 ns
tf Fall time 80% to 20% reference points 30 ns
LVDS(2)
tr Rise slew rate 20% to 80% reference points 0.7 1 V/ns
tf Fall slew rate 80% to 20% reference points 0.7 1 V/ns
tC Clock cycle DCLK_A, LVDS pair 2.5 ns
DCLK_B, LVDS pair 2.5 ns
DCLK_C, LVDS pair 2.5 ns
DCLK_D, LVDS pair 2.5 ns
tW Pulse duration DCLK_A, LVDS pair 1.19 1.25 ns
DCLK_B, LVDS pair 1.19 1.25 ns
DCLK_C, LVDS pair 1.19 1.25 ns
DCLK_D, LVDS pair 1.19 1.25 ns
tSu Setup time D_A(15:0) before DCLK_A, LVDS pair 0.275 ns
D_B(15:0) before DCLK_B, LVDS pair 0.275 ns
D_C(15:0) before DCLK_C, LVDS pair 0.275 ns
D_D(15:0) before DCLK_D, LVDS pair 0.275 ns
SCTRL_A before DCLK_A, LVDS pair 0.275 ns
SCTRL_B before DCLK_B, LVDS pair 0.275 ns
SCTRL_C before DCLK_C, LVDS pair 0.275 ns
SCTRL_D before DCLK_D, LVDS pair 0.275 ns
th Hold time D_A(15:0) after DCLK_A, LVDS pair 0.195 ns
D_B(15:0) after DCLK_B, LVDS pair 0.195 ns
D_C(15:0) after DCLK_C, LVDS pair 0.195 ns
D_D(15:0) after DCLK_D, LVDS pair 0.195 ns
SCTRL_A after DCLK_A, LVDS pair 0.195 ns
SCTRL_B after DCLK_B, LVDS pair 0.195 ns
SCTRL_C after DCLK_C, LVDS pair 0.195 ns
SCTRL_D after DCLK_D, LVDS pair 0.195 ns
tSKEW Skew time Channel B relative to channel A (3)(4) –1.25 1.25 ns
tSKEW Skew time Channel D relative to channel C(5)(6), LVDS pair –1.25 1.25 ns
(1) See the specifications for rise time and fall time for SCP.
(2) See the specifications the for timing requirements for LVDS.
(3) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).
(4) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).
(5) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and D_CP(15:0).
(6) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and D_DP(15:0).