JAJSJ44C may   2020  – july 2023 DLP4710LC

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1.      46
      2. 8.2.1 Design Requirements
      3. 8.2.2 Detailed Design Procedure
      4. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3 Power Supply Sequencing Requirements

GUID-8EE92B5A-A3E0-4D0F-B57F-BD714B944F58-low.gif
DLP display controller software controls start of DMD operation
Mirror park sequence starts
Mirror park sequence ends. DLP PMIC/LED driver disables VBIAS, VOFFSET, and VRESET.
Power off.
Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.
When system power is interrupted, the ASIC driver initiates hardware the power-down sequence, that disables VBIAS, VRESET and VOFFSET after the micromirror park sequence is complete. Software the power-down sequence, disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control.
To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Recommended Operating ConditionsRecommended Operating ConditionsRecommended Operating ConditionsRecommended Operating Conditions.
Drawing is not to scale and details are omitted for clarity.
Figure 9-1 Power Supply Sequencing Requirements
Table 9-1 Power-Up Sequence Delay Requirement
PARAMETERMINMAX UNIT
tDELAYDelay requirement from VOFFSET power up to VBIAS power up2 ms
VOFFSETSupply voltage level during power–up sequence delay (see Figure 9-2)6V
VBIASSupply voltage level during power–up sequence delay (see Figure 9-2)6V
GUID-091BB8A4-8766-45B0-B32D-439EE6031EDD-low.gif
Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.
Figure 9-2 Power-Up Sequence Delay Requirement