The DLP550HE DMD is part of a chipset that is controlled by the DLPC4420 display controller in conjunction with the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the DLP550HE DMD. The DLP550HE DMD board is a high-speed multilayer PCB, with primarily high-speed digital logic utilizing dual edge clock rates up to about 400MHz for DMD LVDS signals. The remaining traces are comprised of low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET and MBRST[0:15]. Solid planes are required for DMD_P3P3V(3.3V) and Ground. The target impedance for the PCB is 50Ω ±10% with the LVDS traces being 100Ω ±10% differential. TI recommends using an 8-layer stack-up as described in Table 9-1.