JAJSQ48 april   2023 DLP550HE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-8033F14E-59F9-42E2-8602-5CABF71DED18-low.gifFigure 5-1 FYA Package149-PinBottom View
Table 5-1 Pin Functions
PIN NET LENGTH (mils) SIGNAL TYPE(1) DESCRIPTION
NAME NO.
DATA INPUTS
D_AN(1) G20 760.78 LVDS I LVDS pair for Data Bus A
D_AN(3) H19 760.73
D_AN(5) F18 760.73
D_AN(7) E18 760.77
D_AN(9) C20 760.67
D_AN(11) B18 760.68
D_AN(13) A20 760.77
D_AN(15) B19 760.79
D_AP(1) H20 760.86
D_AP(3) G19 760.76
D_AP(5) G18 760.81
D_AP(7) D18 760.81
D_AP(9) D20 760.74
D_AP(11) A18 760.77
D_AP(13) B20 760.77
D_AP(15) A19 760.75
D_BN(1) K20 760.72 LVDS I LVDS pair for Data Bus B
D_BN(3) J19 760.79
D_BN(5) L18 760.77
D_BN(7) M18 760.78
D_BN(9) P20 760.76
D_BN(11) R18 760.78
D_BN(13) T20 760.78
D_BN(15) R19 760.77
D_BP(1) J20 760.8
D_BP(3) K19 760.82
D_BP(5) K18 760.85
D_BP(7) N18 760.81
D_BP(9) N20 760.83
D_BP(11) T18 760.8
D_BP(13) R20 760.72
D_BP(15) T19 760.77
DCLK_AN D19 760.73 I LVDS pair for Data Clock A
DCLK_AP E19 760.8
DCLK_BN N19 760.72 I LVDS pair for Data Clock B
DCLK_BP M19 760.8
DATA CONTROL INPUTS
SCTRL_AN F20 760.78 I LVDS pair for Serial Control (Sync) A
SCTRL_AP E20 760.7
SCTRL_BN L20 760.83 I LVDS pair for Serial Control (Sync) B
SCTRL_BP M20 760.78
MICROMIRROR BIAS RESET INPUTS
MBRST(0) C3 I Nonlogic compatible Micromirror Bias Reset signals. Connected directly to the array of pixel micromirrors. Used to hold or release the micromirrors. Bond Pads connect to an internal pulldown resistor.
MBRST(1) D2
MBRST(2) D3
MBRST(3) E2
MBRST(4) G3
MBRST(5) E1
MBRST(6) G2
MBRST(7) G1
MBRST(8) N3
MBRST(9) M2
MBRST(10) M3
MBRST(11) L2
MBRST(12) J3
MBRST(13) L1
MBRST(14) J2
MBRST(15) J1 NC Unused extra pin. Bond Pad connects to an internal pulldown resistor. Do not connect on DLP® system board.
SCP CONTROL
SCPCLK A8 I Serial Communications Port Clock. Bond Pad connects to an internal pulldown circuit.
SCPDI A5 I Serial Communications Port Data. Bond Pad connects to an internal pulldown circuit.
SCPENZ B7 I Active low serial communications port enable. Bond pad connects to an internal pulldown circuit.
SCPDO A9 O Serial communications port output
OTHER SIGNALS
EVCC A3 P Do not connect on the DLP® system board.
MODE_A A4 I Data Bandwidth Mode Select. Bond Pad connects to an internal pulldown circuit. Refer to Table 5-2 for DLP® system board connection information.
PWRDNZ B9 I Active Low Device Reset. Bond Pad connects to an internal pulldown circuit.
POWER
VCC(2) B11, B12, B13, B16, R12, R13, R16, R17 P Power supply for low voltage CMOS logic. Power supply for normal high voltage at micromirror address electrodes
VCCI(2) A12, A14, A16, T12, T14, T16 P Power supply for low voltage CMOS LVDS interface
VCC2(2) C1, D1, M1, N1 P Power supply for high voltage CMOS logic. Power supply for stepped high voltage at micromirror address electrodes
VSS (Ground)(3) A6, A11, A13, A15, A17, B4, B5, B8, B14, B15, B17, C2, C18, C19, F1, F2, F19, H1, H2, H3, H18, J18, K1, K2, L19, N2, P18, P19, R4, R9, R14, R15, T7, T13, T15, T17 P Common Return for all power
RESERVED SIGNALS
RESERVED_FC R7 I Connect to GND on the DLP® system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_FD R8 I Connect to GND on the DLP® system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_PFE T8 I Connect to ground on the DLP® system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_STM B6 I Connect to GND on the DLP® system board. Bond Pad connects to an internal pulldown circuit.
RESERVED_TP0 R10 I Do not connect on the DLP® system board.
RESERVED_TP1 T11 I Do not connect on the DLP® system board.
RESERVED_TP2 R11 I Do not connect on the DLP® system board.
RESERVED_BA T10 O Do not connect on the DLP® system board.
RESERVED_BB A10 O Do not connect on the DLP® system board.
RESERVED_RA1 T9 O Do not connect on the DLP® system board.
RESERVED_RB1 A7 O Do not connect on the DLP® system board.
RESERVED_TS B10 O Do not connect on the DLP® system board.
RESERVED_A(0) T2 NC Do not connect on the DLP® system board.
RESERVED_A(1) T3
RESERVED_A(2) R3
RESERVED_A(3) T4
RESERVED_M(0) R2 NC Do not connect on the DLP® system board.
RESERVED_M(1) P1 NC Do not connect on the DLP® system board.
RESERVED_S(0) T1 NC Do not connect on the DLP® system board.
RESERVED_S(1) R1 NC Do not connect on the DLP® system board.
RESERVED_IRQZ T6 NC Do not connect on the DLP® system board.
RESERVED_OEZ R5 NC Do not connect on the DLP® system board.
RESERVED_RSTZ R6 NC Do not connect on the DLP® system board.
RESERVED_STR T5 NC Do not connect on the DLP® system board.
RESERVED_STR T5 NC Do not connect on the DLP® system board.
RESERVED_VB E3, F3, K3, L3 NC Do not connect on the DLP® system board.
RESERVED_VR B2, B3, P2, P3 NC Do not connect on the DLP® system board.
(1) I = Input, O = Output, G = Ground, A = Analog, P = Power, NC = No Connect.
(2) Power supply pins required for all DMD operating modes are VSS, VCC, VCCI, and VCC2.
(3) VSS must be connected for proper DMD operation.
Table 5-2 Data Bus LVDS Pairs versus MODE_A
MODE_A D_A & D_B
GND (1, 3, 5, 7, 9, 11, 13, 15)
VCC (3, 7, 11, 15)
  1. DLP® ASICs that drive data to the DMD typically do not support every mode shown in Table 5-2.