JAJSQ48A April   2023  – January 2025 DLP550HE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MIN NOM MAX UNIT
VOLTAGE SUPPLY
VCC Supply voltage for LVCMOS core logic(1) 3.0 3.3 3.6 V
VCCI Supply voltage for LVDS interface(1) 3.0 3.3 3.6 V
VOFFSET Micromirror electrode and HVCMOS voltage(1)(2) 7.25 7.5 7.75 V
VMBRST Micromirror clocking pulse voltages(1) –27 26.5 V
|VCCI–VCC| Supply voltage delta (absolute value)(3) 0.3 V
LVCMOS INTERFACE
VIH High level input voltage 1.7 2.5 VCC + 0.3 V
VIL Low level input voltage –0.3 0.7 V
IOH High level output current at VOH = 2.4 V –30 mA
IOL Low level output current at VOL = 0.4 V 25 mA
tPWRDNZ PWRDNZ pulse width(4) 10 ns
SCP INTERFACE
ƒSCPCLK SCP clock frequency(5) 50 500 kHz
tSCP_PD Propagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO(6) 0 900 ns
tSCP_DS SCPDI clock setup time (before SCPCLK falling-edge)(6) 800 ns
tSCP_DH SCPDI hold time (after SCPCLK falling-edge)(6) 900 ns
tSCP_NEG_ENZ Time between falling-edge of SCPENZ and the rising-edge of SCPCLK(5) 1 us
SCP_POS_ENZ Time between falling-edge of SCPCLK and the rising-edge of SCPENZ 1 us
tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tristate) 192/ƒDCLK s
tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 1 1/ƒscpclk
tr Rise time (20% to 80%) 200 ns
tf Fall time (80% to 20%) 200 ns
LVDS INTERFACE
ƒCLOCK Clock frequency for LVDS interface, DCLK_A and DCLK_B(7) 200 230 MHz
|VID| Input differential voltage (absolute value)(8) 100 400 600 mV
VCM Common mode voltage(8) 1200 mV
VLVDS LVDS voltage(8) 0 1900 mV
tr Rise Time (20% to 80%) 100 400 ns
tf Fall time (80% to 20%) 100 400 ns
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 10 ns
ZIN Internal differential termination resistance 95 105 Ω
ENVIRONMENT
TARRAY Array temperature, long-term operational(9)(10)(11) 10 40 to 70 °C
Array temperature, short-term operational, 500-hr max(10)(13) 0 10 °C
TWINDOW Window temperature, operational(14) 85 °C
|TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(15) 14 °C
TDP-AVG Average dew point temperature (non-condensing)(16)

28

 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(17) 28

36

 °C
CTELR Cumulative time in elevated dew point temperature range 24 months
SOLID STATE ILLUMINATION
ILLUV Illumination power at wavelengths < 410 nm(9)(19) 10 mW/cm2
ILLVIS Illumination power at wavelengths ≥ 410 nm and ≤ 800 nm (18)(19) 23.7 W/cm2
ILLIR Illumination power at wavelengths > 800 nm(19) 10 mW/cm2
ILLBLU Illumination power at wavelengths ≥ 410 nm and ≤ 475 nm(18)(19) 7.5 W/cm2
ILLBLU1 Illumination power at wavelengths ≥ 410 nm and ≤ 440 nm (18)(19) 1.3 W/cm2
LAMP ILLUMINATION
ILLUV Illumination power at wavelengths < 395 nm(9)(19) 2.0 mW/cm2
ILLVIS Illumination power at wavelengths ≥ 395 nm and ≤ 800 nm(18)(19) 23.7 W/cm2
ILLIR Illumination power at wavelengths > 800 nm(19) 10 mW/cm2
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. See Section 8.
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(5) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(6) See Figure 5-2.
(7) See LVDS Timing Requirements in Section 5.8 and Figure 5-6.
(8) Refer to Figure 5-5.
(9) Simultaneous exposure of the DMD to the maximum Section 5.4 for temperature and UV illumination reduces device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 6-1 and the package Section 5.5 using the calculation in Section 6.6.
(11) Long-term is defined as the usable life of the device.
(13) Short-term is defined as cumulative time over the usable life of the device.
(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 6-1 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 6-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.
(16) The average over time (including storage and operating) that the device is not in the "elevated dew point temperature range."
(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
(18) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).
(19) To calculate see Section 6.7.
DLP550HE Max Recommended Array Temperature—Derating Curve Figure 5-1 Max Recommended Array Temperature—Derating Curve