JAJSNB4 February   2022 DLP5531A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     11
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     15
    10. 6.8  Switching Characteristics
    11.     17
    12. 6.9  System Mounting Interface Loads
    13.     19
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     21
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Temperature Rise Through the Package for Heatsink Design
      2. 7.6.2 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-D2649BEB-7201-4736-A765-A686EC3C4C90-low.gifFigure 5-1 FYS Package
149-Pin CPGA
Bottom View
Pin Functions - Connector Pins
PINTYPESIGNALDATA RATEDESCRIPTION
NAMENO.
DATA INPUTS
D_AN(0)L2ISubLVDSDoubleData, Negative
D_AN(1)K2ISubLVDSDoubleData, Negative
D_AN(2)J2ISubLVDSDoubleData, Negative
D_AN(3)H2ISubLVDSDoubleData, Negative
D_AN(4)F2ISubLVDSDoubleData, Negative
D_AN(5)E2ISubLVDSDoubleData, Negative
D_AN(6)D2ISubLVDSDoubleData, Negative
D_AN(7)C2ISubLVDSDoubleData, Negative
D_AP(0)L1ISubLVDSDoubleData, Positive
D_AP(1)K1ISubLVDSDoubleData, Positive
D_AP(2)J1ISubLVDSDoubleData, Positive
D_AP(3)H1ISubLVDSDoubleData, Positive
D_AP(4)F1ISubLVDSDoubleData, Positive
D_AP(5)E1ISubLVDSDoubleData, Positive
D_AP(6)D1ISubLVDSDoubleData, Positive
D_AP(7)C1ISubLVDSDoubleData, Positive
D_BN(0)K19ISubLVDSDoubleData, Negative
D_BN(1)J19ISubLVDSDoubleData, Negative
D_BN(2)H19ISubLVDSDoubleData, Negative
D_BN(3)G19ISubLVDSDoubleData, Negative
D_BN(4)E19ISubLVDSDoubleData, Negative
D_BN(5)D19ISubLVDSDoubleData, Negative
D_BN(6)C19ISubLVDSDoubleData, Negative
D_BN(7)B19ISubLVDSDoubleData, Negative
D_BP(0)K20ISubLVDSDoubleData, Positive
D_BP(1)J20ISubLVDSDoubleData, Positive
D_BP(2)H20ISubLVDSDoubleData, Positive
D_BP(3)G20ISubLVDSDoubleData, Positive
D_BP(4)E20ISubLVDSDoubleData, Positive
D_BP(5)D20ISubLVDSDoubleData, Positive
D_BP(6)C20ISubLVDSDoubleData, Positive
D_BP(7)B20ISubLVDSDoubleData, Positive
DCLK_ANG2ISubLVDSDoubleClock, Negative
DCLK_APG1ISubLVDSDoubleClock, Positive
DCLK_BNF19ISubLVDSDoubleClock, Negative
DCLK_BPF20ISubLVDSDoubleClock, Positive
LS_CLKNR3ISubLVDSSingleClock for Low Speed Interface, Negative
LS_CLKPT3ISubLVDSSingleClock for Low Speed Interface, Positive
LS_WDATANR2ISubLVDSSingleWrite Data for Low Speed Interface, Negative
LS_WDATAPT2ISubLVDSSingleWrite Data for Low Speed Interface, Positive
CONTROL INPUTS
DMD_DEN_ARSTZT10ILPSDRAsynchronous Reset Active Low. Logic High Enables DMD.
LS_RDATA_AT5OLPSDRSingleRead Data for Low Speed Interface
LS_RDATA_BT6OLPSDRSingleRead Data for Low Speed Interface
TEMPERATURE SENSE DIODE
TEMP_NP1OCalibrated temperature diode used to assist accurate temperature measurements of DMD die.
TEMP_PN1I
RESERVED PINS
VCCHA8GroundReserved Pin. Connect to Ground.
VCCHA9Ground
VCCHA10Ground
VCCHB8Ground
VCCHB9Ground
VCCHB10Ground
VSSHA11GroundReserved Pin. Connect to Ground.
VSSHA12Ground
VSSHA13Ground
VSSHB11Ground
VSSHB12Ground
VSSHB13Ground
POWER
VBIAST7PowerSupply voltage for positive bias level at micromirrors.
VBIAST15Power
VOFFSETT9PowerSupply voltage for High Voltage CMOS core logic. Supply voltage for offset level at micromirrors.
VOFFSETT13Power
VOFFSETA5Power
VOFFSETB5Power
VOFFSETA16Power
VOFFSETB16Power
VRESETT8PowerSupply voltage for negative reset level at micromirrors.
VRESETT14Power
VDDR4PowerSupply voltage for Low Voltage CMOS core logic; for LPSDR inputs; for normal high level at micromirror address electrodes.
VDDR10Power
VDDR11Power
VDDR20Power
VDDN2Power
VDDM20Power
VDDL3Power
VDDK18Power
VDDH3Power
VDDG18Power
VDDE3Power
VDDD18Power
VDDC3Power
VDDA6Power
VDDA18Power
VDDIT4PowerSupply voltage for SubLVDS receivers.
VDDIR1Power
VDDIM3Power
VDDIL18Power
VDDIJ3Power
VDDIH18Power
VDDIF3Power
VDDIE18Power
VDDIB3Power
VDDIB18Power
VSST1GroundCommon return. Ground for all power.
VSST16Ground
VSST19Ground
VSST20Ground
VSSR5Ground
VSSR6Ground
VSSR7Ground
VSSR8Ground
VSSR9Ground
VSSR13Ground
VSSR14Ground
VSSR15Ground
VSSP2Ground
VSSP3Ground
VSSP20Ground
VSSN19Ground
VSSN20Ground
VSSM1Ground
VSSM2Ground
VSSL19Ground
VSSL20Ground
VSSK3Ground
VSSJ18Ground
VSSG3Ground
VSSF18Ground
VSSD3Ground
VSSC18Ground
VSSB2Ground
VSSB4Ground
VSSB15Ground
VSSB17Ground
VSSA3Ground
VSSA4Ground
VSSA7Ground
VSSA15Ground
VSSA17Ground
VSSA19Ground
VSSA20Ground
Pin Functions - Test Pads
NUMBERSYSTEM BOARD
T11Do not connect
T12Do not connect
T17Do not connect
T18Do not connect
R12Do not connect
R16Do not connect
R17Do not connect
R18Do not connect
R19Do not connect
P18Do not connect
P19Do not connect
N3Do not connect
N18Do not connect
M18Do not connect
M19Do not connect
B6Do not connect
B7Do not connect
B14Do not connect
A14Do not connect