JAJSNB4 February 2022 DLP5531A-Q1
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLY VOLTAGE RANGE | ||||||
VDD | Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface |
1.7 | 1.8 | 1.95 | V | |
VDDI | Supply voltage for SubLVDS receivers | 1.7 | 1.8 | 1.95 | V | |
VOFFSET | Supply voltage for HVCMOS and micromirror electrode | 8.25 | 8.5 | 8.75 | V | |
VBIAS | Supply voltage for mirror electrode | 15.5 | 16 | 16.5 | V | |
VRESET | Supply voltage for micromirror electrode | –9.5 | –10 | –10.5 | V | |
| VDDI–VDD | | Supply voltage delta (absolute value) | 0.3 | V | |||
| VBIAS–VOFFSET | | Supply voltage delta (absolute value) | 8.75 | V | |||
CLOCK FREQUENCY | ||||||
ƒmax | Clock frequency for low speed interface LS_CLK | 120 | MHz | |||
ƒmax | Clock frequency for high speed interface DCLK | 600 | MHz | |||
Duty cycle distortion DCLK | 44% | 56% | ||||
SUBLVDS INTERFACE | ||||||
| VID | | SubLVDS input differential voltage (absolute value)(2) | 150 | 250 | 350 | mV | |
VCM | Common mode voltage (2) | 700 | 900 | 1100 | mV | |
ZLINE | Line differential impedance (PWB/trace) | 90 | 100 | 110 | Ω | |
ZIN | Internal differential termination resistance(3) | 80 | 100 | 120 | Ω | |
ENVIRONMENTAL | ||||||
TARRAY | Operating DMD array temperature(5) | –40 | 105 | °C | ||
ILLUV | Illumination, wavelength < 395 nm (4) | 2 | mW/cm 2 | |||
ILLOVERFILL | Illumination overfill maximum heat load in area shown in Figure 6-1 | 28 | mW/mm 2 |