JAJSNB4 February   2022 DLP5531A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     11
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     15
    10. 6.8  Switching Characteristics
    11.     17
    12. 6.9  System Mounting Interface Loads
    13.     19
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     21
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Temperature Rise Through the Package for Heatsink Design
      2. 7.6.2 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 DMD Handling
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Absolute Maximum Ratings

see (1)
MIN NOM MAX UNIT
SUPPLY VOLTAGE
VDD Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low speed interface		 –0.5 2.3 V
VDDI Supply voltage for SubLVDS receivers –0.5 2.3 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode –0.5 8.75 V
VBIAS Supply voltage for micromirror electrode –0.5 17 V
VRESET Supply voltage for micromirror electrode –11 0.5 V
| VDDI–VDD | Supply voltage delta (absolute value) 0.3 V
| VBIAS–VOFFSET | Supply voltage delta (absolute value) 8.75 V
| VBIAS–VRESET | Supply voltage delta (absolute value) 28 V
INPUT VOLTAGE
Input voltage for other inputs LPSDR –0.5 VDD + 0.5 V
Input voltage for other inputs SubLVDS –0.5 VDDI + 0.5 V
INPUT PINS
| VID | SubLVDS input differential voltage (absolute value) 810 mV
IID SubLVDS input differential current 10 mA
TEMPERATURE DIODE
ITEMP_DIODE Max current source into temperature diode 120 μA
ENVIRONMENTAL
ILLOVERFILL Illumination overfill maximum heat load in area shown in Figure 6-1 37 mW/mm2
TARRAY Operating DMD array temperature –40 105 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device reliability.