JAJSLM7A September 2020 – April 2021 DLP5533A-Q1
PRODUCTION DATA
PIN | TYPE | SIGNAL | DATA RATE | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
DATA INPUTS | |||||
D_AN(0) | L2 | I | SubLVDS | Double | Data, Negative |
D_AN(1) | K2 | I | SubLVDS | Double | Data, Negative |
D_AN(2) | J2 | I | SubLVDS | Double | Data, Negative |
D_AN(3) | H2 | I | SubLVDS | Double | Data, Negative |
D_AN(4) | F2 | I | SubLVDS | Double | Data, Negative |
D_AN(5) | E2 | I | SubLVDS | Double | Data, Negative |
D_AN(6) | D2 | I | SubLVDS | Double | Data, Negative |
D_AN(7) | C2 | I | SubLVDS | Double | Data, Negative |
D_AP(0) | L1 | I | SubLVDS | Double | Data, Positive |
D_AP(1) | K1 | I | SubLVDS | Double | Data, Positive |
D_AP(2) | J1 | I | SubLVDS | Double | Data, Positive |
D_AP(3) | H1 | I | SubLVDS | Double | Data, Positive |
D_AP(4) | F1 | I | SubLVDS | Double | Data, Positive |
D_AP(5) | E1 | I | SubLVDS | Double | Data, Positive |
D_AP(6) | D1 | I | SubLVDS | Double | Data, Positive |
D_AP(7) | C1 | I | SubLVDS | Double | Data, Positive |
D_BN(0) | K19 | I | SubLVDS | Double | Data, Negative |
D_BN(1) | J19 | I | SubLVDS | Double | Data, Negative |
D_BN(2) | H19 | I | SubLVDS | Double | Data, Negative |
D_BN(3) | G19 | I | SubLVDS | Double | Data, Negative |
D_BN(4) | E19 | I | SubLVDS | Double | Data, Negative |
D_BN(5) | D19 | I | SubLVDS | Double | Data, Negative |
D_BN(6) | C19 | I | SubLVDS | Double | Data, Negative |
D_BN(7) | B19 | I | SubLVDS | Double | Data, Negative |
D_BP(0) | K20 | I | SubLVDS | Double | Data, Positive |
D_BP(1) | J20 | I | SubLVDS | Double | Data, Positive |
D_BP(2) | H20 | I | SubLVDS | Double | Data, Positive |
D_BP(3) | G20 | I | SubLVDS | Double | Data, Positive |
D_BP(4) | E20 | I | SubLVDS | Double | Data, Positive |
D_BP(5) | D20 | I | SubLVDS | Double | Data, Positive |
D_BP(6) | C20 | I | SubLVDS | Double | Data, Positive |
D_BP(7) | B20 | I | SubLVDS | Double | Data, Positive |
DCLK_AN | G2 | I | SubLVDS | Double | Clock, Negative |
DCLK_AP | G1 | I | SubLVDS | Double | Clock, Positive |
DCLK_BN | F19 | I | SubLVDS | Double | Clock, Negative |
DCLK_BP | F20 | I | SubLVDS | Double | Clock, Positive |
LS_CLKN | R3 | I | SubLVDS | Single | Clock for Low Speed Interface, Negative |
LS_CLKP | T3 | I | SubLVDS | Single | Clock for Low Speed Interface, Positive |
LS_WDATAN | R2 | I | SubLVDS | Single | Write Data for Low Speed Interface, Negative |
LS_WDATAP | T2 | I | SubLVDS | Single | Write Data for Low Speed Interface, Positive |
CONTROL INPUTS | |||||
DMD_DEN_ARSTZ | T10 | I | LPSDR | Asynchronous Reset Active Low. Logic High Enables DMD. | |
LS_RDATA_A | T5 | O | LPSDR | Single | Read Data for Low Speed Interface |
LS_RDATA_B | T6 | O | LPSDR | Single | Read Data for Low Speed Interface |
TEMPERATURE SENSE DIODE | |||||
TEMP_N | P1 | O | Calibrated temperature diode used to assist accurate temperature measurements of DMD die. | ||
TEMP_P | N1 | I | |||
RESERVED PINS | |||||
VCCH | A8 | Ground | Reserved Pin. Connect to Ground. | ||
VCCH | A9 | Ground | |||
VCCH | A10 | Ground | |||
VCCH | B8 | Ground | |||
VCCH | B9 | Ground | |||
VCCH | B10 | Ground | |||
VSSH | A11 | Ground | Reserved Pin. Connect to Ground. | ||
VSSH | A12 | Ground | |||
VSSH | A13 | Ground | |||
VSSH | B11 | Ground | |||
VSSH | B12 | Ground | |||
VSSH | B13 | Ground | |||
POWER | |||||
VBIAS | T7 | Power | Supply voltage for positive bias level at micromirrors. | ||
VBIAS | T15 | Power | |||
VOFFSET | T9 | Power | Supply voltage for High Voltage CMOS core logic. Supply voltage for offset level at micromirrors. | ||
VOFFSET | T13 | Power | |||
VOFFSET | A5 | Power | |||
VOFFSET | B5 | Power | |||
VOFFSET | A16 | Power | |||
VOFFSET | B16 | Power | |||
VRESET | T8 | Power | Supply voltage for negative reset level at micromirrors. | ||
VRESET | T14 | Power | |||
VDD | R4 | Power | Supply voltage for Low Voltage CMOS core logic; for LPSDR inputs; for normal high level at micromirror address electrodes. | ||
VDD | R10 | Power | |||
VDD | R11 | Power | |||
VDD | R20 | Power | |||
VDD | N2 | Power | |||
VDD | M20 | Power | |||
VDD | L3 | Power | |||
VDD | K18 | Power | |||
VDD | H3 | Power | |||
VDD | G18 | Power | |||
VDD | E3 | Power | |||
VDD | D18 | Power | |||
VDD | C3 | Power | |||
VDD | A6 | Power | |||
VDD | A18 | Power | |||
VDDI | T4 | Power | Supply voltage for SubLVDS receivers. | ||
VDDI | R1 | Power | |||
VDDI | M3 | Power | |||
VDDI | L18 | Power | |||
VDDI | J3 | Power | |||
VDDI | H18 | Power | |||
VDDI | F3 | Power | |||
VDDI | E18 | Power | |||
VDDI | B3 | Power | |||
VDDI | B18 | Power | |||
VSS | T1 | Ground | Common return. Ground for all power. | ||
VSS | T16 | Ground | |||
VSS | T19 | Ground | |||
VSS | T20 | Ground | |||
VSS | R5 | Ground | |||
VSS | R6 | Ground | |||
VSS | R7 | Ground | |||
VSS | R8 | Ground | |||
VSS | R9 | Ground | |||
VSS | R13 | Ground | |||
VSS | R14 | Ground | |||
VSS | R15 | Ground | |||
VSS | P2 | Ground | |||
VSS | P3 | Ground | |||
VSS | P20 | Ground | |||
VSS | N19 | Ground | |||
VSS | N20 | Ground | |||
VSS | M1 | Ground | |||
VSS | M2 | Ground | |||
VSS | L19 | Ground | |||
VSS | L20 | Ground | |||
VSS | K3 | Ground | |||
VSS | J18 | Ground | |||
VSS | G3 | Ground | |||
VSS | F18 | Ground | |||
VSS | D3 | Ground | |||
VSS | C18 | Ground | |||
VSS | B2 | Ground | |||
VSS | B4 | Ground | |||
VSS | B15 | Ground | |||
VSS | B17 | Ground | |||
VSS | A3 | Ground | |||
VSS | A4 | Ground | |||
VSS | A7 | Ground | |||
VSS | A15 | Ground | |||
VSS | A17 | Ground | |||
VSS | A19 | Ground | |||
VSS | A20 | Ground |
NUMBER | SYSTEM BOARD | ||
---|---|---|---|
T11 | Do not connect | ||
T12 | Do not connect | ||
T17 | Do not connect | ||
T18 | Do not connect | ||
R12 | Do not connect | ||
R16 | Do not connect | ||
R17 | Do not connect | ||
R18 | Do not connect | ||
R19 | Do not connect | ||
P18 | Do not connect | ||
P19 | Do not connect | ||
N3 | Do not connect | ||
N18 | Do not connect | ||
M18 | Do not connect | ||
M19 | Do not connect | ||
B6 | Do not connect | ||
B7 | Do not connect | ||
B14 | Do not connect | ||
A14 | Do not connect |