JAJSLM7A September   2020  – April 2021 DLP5533A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     Illumination Overfill Diagram
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     Electrical and Timing Diagrams
    10. 6.8  Switching Characteristics
    11.     LPSDR and Test Load Circuit Diagrams
    12. 6.9  System Mounting Interface Loads
    13.     System Interface Loads Diagram
    14. 6.10 Physical Characteristics of the Micromirror Array
    15.     Array Physical Characteristics Diagram
    16. 6.11 Micromirror Array Optical Characteristics
    17. 6.12 Window Characteristics
    18. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sub-LVDS Data Interface
      2. 7.3.2 Low Speed Interface for Control
      3. 7.3.3 DMD Voltage Supplies
      4. 7.3.4 Asynchronous Reset
      5. 7.3.5 Temperature Sensing Diode
        1. 7.3.5.1 Temperature Sense Diode Theory
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Temperature Rise Through the Package for Heatsink Design
      2. 7.6.2 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Overview
      2. 8.2.2 Reference Design
      3. 8.2.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 DMD Handling
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
SUPPLY VOLTAGE RANGE
VDD Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface		 1.7 1.8 1.95 V
VDDI Supply voltage for SubLVDS receivers 1.7 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode 8.25 8.5 8.75 V
VBIAS Supply voltage for mirror electrode 15.5 16 16.5 V
VRESET Supply voltage for micromirror electrode –9.5 –10 –10.5 V
| VDDI–VDD | Supply voltage delta (absolute value) 0.3 V
| VBIAS–VOFFSET | Supply voltage delta (absolute value) 8.75 V
CLOCK FREQUENCY
ƒmax Clock frequency for low speed interface LS_CLK 120 MHz
ƒmax Clock frequency for high speed interface DCLK 600 MHz
Duty cycle distortion DCLK 44% 56%
SUBLVDS INTERFACE
| VID | SubLVDS input differential voltage (absolute value)(2) 150 250 350 mV
VCM Common mode voltage (2) 700 900 1100 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance(3) 80 100 120 Ω
ENVIRONMENTAL
TARRAY Operating DMD array temperature(5) –40 105 °C
ILLUV Illumination, wavelength < 395 nm (4) 2 mW/cm 2
ILLOVERFILL Illumination overfill maximum heat load in area shown in Figure 6-1 28 mW/mm 2
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) See Figure 6-6 and Figure 6-7
(3) See Figure 6-8
(4) The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously.
(5) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.