JAJSIM5 データシート

JAJSIM5A November 2020 – June 2022 DLP670S

PRODUCTION DATA

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メカニカル・データ（パッケージ｜ピン）

FYR|350
- MCPG033

サーマルパッド・メカニカル・データ

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6.8 Timing Requirements

			MIN	NOM	MAX	UNIT
SCP⁽¹⁾
t_r	Rise time	20% to 80% reference points			30	ns
t_f	Fall time	80% to 20% reference points			30	ns
LVDS⁽²⁾
t_r	Rise slew rate	20% to 80% reference points	0.7	1		V/ns
t_f	Fall slew rate	80% to 20% reference points	0.7	1		V/ns
t_C	Clock Cycle	DCLK_A, LVDS pair	2.5			ns
t_C	Clock Cycle	DCLK_B, LVDS pair	2.5			ns
t_C	Clock Cycle	DCLK_C, LVDS pair	2.5			ns
t_C	Clock Cycle	DCLK_D, LVDS pair	2.5			ns
t_W	Pulse Width	DCLK_A LVDS pair	1.19	1.25		ns
t_W	Pulse Width	DCLK_B LVDS pair	1.19	1.25		ns
t_W	Pulse Width	DCLK_C LVDS pair	1.19	1.25		ns
t_W	Pulse Width	DCLK_D LVDS pair	1.19	1.25		ns
t_Su	Setup Time	D_A(15:0) before DCLK_A, LVDS pair	0.325			ns
t_Su	Setup Time	D_B(15:0) before DCLK_B, LVDS pair	0.325			ns
t_Su	Setup Time	D_C(15:0) before DCLK_C, LVDS pair	0.325			ns
t_Su	Setup Time	D_D(15:0) before DCLK_D, LVDS pair	0.325			ns
t_Su	Setup Time	SCTRL_A before DCLK_A, LVDS pair	0.325			ns
t_Su	Setup Time	SCTRL_B before DCLK_B, LVDS pair	0.325			ns
t_Su	Setup Time	SCTRL_C before DCLK_C, LVDS pair	0.325			ns
t_Su	Setup Time	SCTRL_D before DCLK_D, LVDS pair	0.325			ns
t_h	Hold Time	D_A(15:0) after DCLK_A, LVDS pair	0.145			ns
t_h	Hold Time	D_B(15:0) after DCLK_B, LVDS pair	0.145			ns
t_h	Hold Time	D_C(15:0) after DCLK_C, LVDS pair	0.145			ns
t_h	Hold Time	D_D(15:0) after DCLK_D, LVDS pair	0.145			ns
t_h	Hold Time	SCTRL_A after DCLK_A, LVDS pair	0.145			ns
t_h	Hold Time	SCTRL_B after DCLK_B, LVDS pair	0.145			ns
t_h	Hold Time	SCTRL_C after DCLK_C, LVDS pair	0.145			ns
t_h	Hold Time	SCTRL_D after DCLK_D, LVDS pair	0.145			ns
LVDS⁽²⁾
t_SKEW	Skew Time	Channel B relative to Channel A⁽³⁾⁽⁴⁾, LVDS pair	–1.25		+1.25	ns
t_SKEW	Skew Time	Channel D relative to Channel C⁽⁵⁾⁽⁶⁾, LVDS pair	–1.25		+1.25	ns

(1) See Figure 6-3 for Rise Time and Fall Time for SCP.

(2) See Figure 6-5 for Timing Requirements for LVDS.

(3) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).

(4) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).

(5) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and D_CP(15:0).

(6) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and D_DP(15:0).

Figure 6-2 SCP Timing Requirements

A. See Section 6.4 for f_SCPCLK, t_{SCP_DS}, t_{SCP_DH} and t_{SCP_PD} specifications.

B. SCPCLK falling–edge capture for SCPDI.

C. SCPCLK rising–edge launch for SCPDO.

D. See Equation 1.

Equation 1.

Figure 6-3 SCP Requirements for Rise and Fall

See Section 6.8 for t_r and t_f specifications and conditions.

Figure 6-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers must use IBIS or other simulation tools to correlate the timing reference load to a system environment.

A. See Equation 2 and Equation 3.

Figure 6-5 LVDS Waveform Requirements

Equation 2.

Equation 3.

See Section 6.4 for V_CM, V_ID, and V_LVDS specifications and conditions.

Figure 6-6 Timing Requirements

Figure 6-7 LVDS Interface Channel Skew Definition

See Section 6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(15:0) and D_N(15:0).