JAJSN06B September   2021  – March 2024 DLP780NE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Timing Requirements
    9.     15
    10. 5.8  System Mounting Interface Loads
    11.     17
    12. 5.9  Micromirror Array Physical Characteristics
    13.     19
    14. 5.10 Micromirror Array Optical Characteristics
    15.     21
    16. 5.11 Window Characteristics
    17. 5.12 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
    3. 10.3 Device Markings
    4. 10.4 Documentation Support
      1. 10.4.1 Related Documentation
    5. 10.5 ドキュメントの更新通知を受け取る方法
    6. 10.6 サポート・リソース
    7. 10.7 Trademarks
    8. 10.8 静電気放電に関する注意事項
    9. 10.9 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20201214-CA0I-RVQB-7JVM-MHPJ5XWSBJNP-low.gif Figure 4-1 FYU Package (350-Pin) Bottom View
Table 4-1 Pin Functions
PIN TYPE(1) PIN DESCRIPTION SIGNAL TYPE TERMINATION
SIGNAL PGA_PAD
LVDS BUS C
D_CN(0) B18 I High-speed differential pair LVDS Differential 100Ω
D_CP(0) B19 I
D_CN(1) H24 I High-speed differential pair Differential 100Ω
D_CP(1) G24 I
D_CN(2) L23 I High-speed differential pair Differential 100Ω
D_CP(2) K23 I
D_CN(3) C18 I High-speed differential pair Differential 100Ω
D_CP(3) C19 I
D_CN(4) A19 I High-speed differential pair Differential 100Ω
D_CP(4) A20 I
D_CN(5) E24 I High-speed differential pair Differential 100Ω
D_CP(5) D24 I
D_CN(6) K25 I High-speed differential pair Differential 100Ω
D_CP(6) J25 I
D_CN(7) C26 I High-speed differential pair Differential 100Ω
D_CP(7) D26 I
D_CN(8) C21 I High-speed differential pair Differential 100Ω
D_CP(8) B21 I
D_CN(9) G25 I High-speed differential pair Differential 100Ω
D_CP(9) F25 I
D_CN(10) A24 I High-speed differential pair Differential 100Ω
D_CP(10) B24 I
D_CN(11) J26 I High-speed differential pair Differential 100Ω
D_CP(11) K26 I
D_CN(12) D25 I High-speed differential pair Differential 100Ω
D_CP(12) C25 I
D_CN(13) E23 I High-speed differential pair Differential 100Ω
D_CP(13) D23 I
D_CN(14) B23 I High-speed differential pair Differential 100Ω
D_CP(14) C23 I
D_CN(15) K24 I High-speed differential pair Differential 100Ω
D_CP(15) L24 I
DCLK_CN H23 I High-speed differential pair Differential 100Ω
DCLK_CP G23 I
SCTRL_CN F26 I High-speed differential pair Differential 100Ω
SCTRL_CP G26 I
LVDS BUS D
D_DN(0) Z18 I High-speed differential pair LVDS Differential 100Ω
D_DP(0) Z19 I
D_DN(1) T24 I High-speed differential pair Differential 100Ω
D_DP(1) U24 I
D_DN(2) N23 I High-speed differential pair Differential 100Ω
D_DP(2) P23 I
D_DN(3) Y18 I High-speed differential pair Differential 100Ω
D_DP(3) Y19 I
D_DN(4) AA19 I High-speed differential pair Differential 100Ω
D_DP(4) AA20 I
D_DN(5) W24 I High-speed differential pair Differential 100Ω
D_DP(5) X24 I
D_DN(6) P25 I High-speed differential pair Differential 100Ω
D_DP(6) R25 I
D_DN(7) Y26 I High-speed differential pair Differential 100Ω
D_DP(7) X26 I
D_DN(8) Y21 I High-speed differential pair Differential 100Ω
D_DP(8) Z21 I
D_DN(9) U25 I High-speed differential pair Differential 100Ω
D_DP(9) V25 I
D_DN(10) AA24 I High-speed differential pair Differential 100Ω
D_DP(10) Z24 I
D_DN(11) R26 I High-speed differential pair Differential 100Ω
D_DP(11) P26 I
D_DN(12) X25 I High-speed differential pair Differential 100Ω
D_DP(12) Y25 I
D_DN(13) W23 I High-speed differential pair Differential 100Ω
D_DP(13) X23 I
D_DN(14) Z23 I High-speed differential pair Differential 100Ω
D_DP(14) Y23 I
D_DN(15) P24 I High-speed differential pair Differential 100Ω
D_DP(15) N24 I
DCLK_DN T23 I High-speed differential pair Differential 100Ω
DCLK_DP U23 I
SCTRL_DN V26 I High-speed differential pair Differential 100Ω
SCTRL_DP U26 I
SCP INTERFACE
SCPCLK U2 I Serial Communications Port CLK LVCMOS Internal pulldown
SCPDI T3 I Serial Communications Data In LVCMOS Internal pulldown
SCPENZ U4 I Serial Communications Port Enable LVCMOS Internal pulldown
SCPDO U3 O Serial Communications Port Output LVCMOS Internal pulldown
OTHER SIGNALS
DMD_PWRDNZ G4 I Chip–Level ResetZ LVCMOS Internal pulldown
N/C G1, H1, J1, J3, J4, K3, P3, R1, R3, R4, T1, U1, V3, D17, X17, K4, P4, F3, G2, H3, W18, G3, W6, W5, Y5, Y4, W15, X15, Z16, Z15, Y16, Y17, Z13, Z12, Y14, Y13, AA10, AA9, Z10, Y10, Z5, Z6, Z9, Z8, W3, X3, X6, Y6, X7, X8, Y8, Y7, X4, W4, Y3, Z3, W11, W10, D4, E4, C3, B3, E15, D15, B16, B15, C16, C17, B13, B12, C14, C13, A10, A9, B10, C10, B5, B6, B9, B8, C4, C5, E5, E6, D7, D8, C8, C7, D3, E3, C6, D6, E11, E10, X16 No Connect
TEMP_N W16 I/O
TEMP_P W17 I/O
MICROMIRROR BIAS RESET INPUTS
MBRST(0) E14 I Mirror actuation signal
MBRST(1) D13 I Mirror actuation signal
MBRST(2) E13 I Mirror actuation signal
MBRST(3) C12 I Mirror actuation signal
MBRST(4) E12 I Mirror actuation signal
MBRST(5) C11 I Mirror actuation signal
MBRST(6) D16 I Mirror actuation signal
MBRST(7) C15 I Mirror actuation signal
MBRST(8) W14 I Mirror actuation signal
MBRST(9) X13 I Mirror actuation signal
MBRST(10) W13 I Mirror actuation signal
MBRST(11) Y12 I Mirror actuation signal
MBRST(12) W12 I Mirror actuation signal
MBRST(13) Y11 I Mirror actuation signal
MBRST(14) Y15 I Mirror actuation signal
POWERS AND GROUNDS
VDD A5, A6, B2, C1, D10, D12, D19, D22, E8, E19, E20, E21, E22, F1, F2, J2, K1, L1, L25, M3, M4, M25, N1, N25, P1, R2, V1, V2, W8, W19, W20, W21, W22, X10, X12, X19, X22, Y1, Z1, Z2, AA2, AA5, AA6 P Low-voltage CMOS core supply
VDDI A7, A8, A11, A16, A17, A18, A21, A22, A23, AA7, AA8, AA11, AA16, AA17, AA18, AA21, AA22, AA23 P I/O supply
VCC2 A3, A4, A25, B26, L26, M26, N26, Z26, AA3, AA4, AA25 P Memory array stepped-up voltage
VSS B4, B7, B11, B14, B17, B20, B22, B25, C2, C9, C20, C22, C24, D1, D2, D5, D9, D11, D14, D18, D20, D21, E1, E2, E7, E9, E16, E17, E18, E25, E26, F4, F23, F24, H2, H4, H25, H26, J23, J24, K2, L2, L3, L4, M1, M2, M23, M24, N2, N3, N4, P2, R23, R24, T2, T4, T25, T26, V4, V23, V24, W1, W2, W7, W9, W25, W26, X1, X2, X5, X9, X11, X14, X18, X20, X21, Y2, Y9, Y20, Y22, Y24, Z4, Z7, Z11, Z14, Z17, Z20, Z22, Z25 G Global ground
(1) I = Input, O = Output, P = Power, G = Ground, NC = No Connect