JAJSP80A November   2022  – September 2023 DLP801RE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5.     12
    6. 6.5  Thermal Information
    7. 6.6  Electrical Characteristics
    8. 6.7  Timing Requirements
    9.     16
    10. 6.8  System Mounting Interface Loads
    11.     18
    12. 6.9  Micromirror Array Physical Characteristics
    13.     20
    14. 6.10 Micromirror Array Optical Characteristics
    15.     22
    16. 6.11 Window Characteristics
    17. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Window Aperture Illumination Overfill Calculation
    9. 7.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
    3. 11.3 Device Markings
    4. 11.4 Documentation Support
      1. 11.4.1 Related Documentation
    5. 11.5 ドキュメントの更新通知を受け取る方法
    6. 11.6 サポート・リソース
    7. 11.7 Trademarks
    8. 11.8 静電気放電に関する注意事項
    9. 11.9 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

9.3 DMD Power Supply Power-Down Procedure

  • During power-down, VDD and VDDI must be supplied until after VCC2 is discharged to within the specified limit of ground. Refer to Section 6.4.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Section 6.1 and in Section 6.4.
  • During power-down, LVCMOS input pins must be less than specified in Section 6.4.
GUID-20210521-CA0I-GPVX-R1ZW-NMFMBH8K3HQT-low.gif Figure 9-1 DMD Power Supply Sequencing Requirements
A. See Pin Configuration and Functions for pin functions.
B. VDD must be up and stable prior to VCC2 powering up.
C. PWRDNZ has two turn on options. Option 1: PWRDNZ does not go high until VDD and VCC2 are up and stable, or Option 2: PWRDNZ must be pulsed low for a minimum of TPWRDNZ, or 10 ns after VDD and VCC2 are up and stable.
D. There is a minimum of TLVDS_ARSTZ, or 2 μs, wait time from PWRDNZ going high for the LVDS receiver to recover.
E. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates the PWRDNZ and disables VCC2.
F. Under power-loss conditions, where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, PWRDNZ goes low.
G. VDD must remain high until after VCC2 goes low.
H. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit in Section 6.4.