JAJSFJ1 May   2018 DLPA4000

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      システム・ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Description
    3. 8.3 Feature Description
      1. 8.3.1 Supply and Monitoring
        1. 8.3.1.1 Supply
        2. 8.3.1.2 Monitoring
          1. 8.3.1.2.1 Block Faults
          2. 8.3.1.2.2 Low Battery and UVLO
          3. 8.3.1.2.3 Thermal Protection
      2. 8.3.2 Illumination
        1. 8.3.2.1 Programmable Gain Block
        2. 8.3.2.2 LDO Illumination
        3. 8.3.2.3 Illumination Driver A
        4. 8.3.2.4 External MOSFETs
          1. 8.3.2.4.1 Gate series resistor (RG)
          2. 8.3.2.4.2 Gate series diode (DG)
          3. 8.3.2.4.3 Gate parallel capacitance (CG)
        5. 8.3.2.5 RGB Strobe Decoder
          1. 8.3.2.5.1 Break Before Make (BBM)
          2. 8.3.2.5.2 Openloop Voltage
          3. 8.3.2.5.3 Transient Current Limit
        6. 8.3.2.6 Illumination Monitoring
          1. 8.3.2.6.1 Power Good
          2. 8.3.2.6.2 RatioMetric Overvoltage Protection
      3. 8.3.3 External Power MOSFET Selection
        1. 8.3.3.1 Threshold Voltage
        2. 8.3.3.2 Gate Charge and Gate Timing
        3. 8.3.3.3 On-resistance RDS(on)
      4. 8.3.4 DMD Supplies
        1. 8.3.4.1 LDO DMD
        2. 8.3.4.2 DMD HV Regulator
        3. 8.3.4.3 DMD/DLPC Buck Converters
        4. 8.3.4.4 DMD Monitoring
          1. 8.3.4.4.1 Power Good
          2. 8.3.4.4.2 Overvoltage Fault
      5. 8.3.5 Buck Converters
        1. 8.3.5.1 LDO Bucks
        2. 8.3.5.2 General Purpose Buck Converters
        3. 8.3.5.3 Buck Converter Monitoring
          1. 8.3.5.3.1 Power Good
          2. 8.3.5.3.2 Overvoltage Fault
      6. 8.3.6 Auxiliary LDOs
      7. 8.3.7 Measurement System
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 SPI
      2. 8.5.2 Interrupt
      3. 8.5.3 Fast-Shutdown in Case of Fault
      4. 8.5.4 Protected Registers
      5. 8.5.5 Writing to EEPROM
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection for General-Purpose Buck Converters
    3. 9.3 System Example With DLPA4000 Internal Block Diagram
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up and Power-Down Timing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LED Driver
        1. 11.1.1.1 PowerBlock Gate Control Isolation
        2. 11.1.1.2 VIN to PowerBlocks
        3. 11.1.1.3 Return Current from LEDs and RSense
        4. 11.1.1.4 RC Snubber
        5. 11.1.1.5 Capacitor Choice
      2. 11.1.2 General Purpose Buck 2
      3. 11.1.3 SPI Connections
      4. 11.1.4 RLIM Routing
      5. 11.1.5 LED Connection
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Over operating free-air temperature range. VIN = 19.5 V, TA = 0 to +40°C, typical values are at TA = 25°C, Configuration according to Typical Application (VIN =19.5 V, IOUT = 32 A, LED, external MOSFETs ) (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLIES
INPUT VOLTAGE
VIN Input voltage range VINA – pin 16(3) 19.5 20 V
VLOW_BAT Low battery warning threshold VINA falling (via 5 bit trim function, 0.5 V steps) 3.9 18.4 V
Hysteresis VINA rising 90 mV
VUVLO UVLO threshold VINA falling (via 5 bit trim function, 0.5 V steps) 3.9 18.4 V
Hysteresis VINA rising 90 mV
VSTARTUP Startup voltage DMD_VBIAS, DMD_VOFFSET, DMD_VRESET loaded with 10 mA 6 V
INPUT CURRENT
IIDLE Idle current IDLE mode, all VIN pins combined 15 µA
ISTD Standby current STANDBY mode, analog, internal supplies and LDOs enabled, DMD, ILLUMINATION and BUCK CONVERTERS disabled. 3.7 mA
IQ_DMD Quiescent current (DMD) Quiescent current DMD block (in addtion to ISTD), VINA + DRST_VIN 0.49 mA
IQ_ILLUM Quiescent current (ILLUM) Quiescent current ILLUM block (in addtion to ISTD), V_openloop= 3 V (0x18, ILLUM_OLV_SEL), VINA + ILLUM_VIN + ILLUM_A_VIN + ILLUM_B_VIN 21 mA
IQ_BUCK Quiescent current
(per BUCK)		 Quiescent current per BUCK converter (in addtion to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 1 V 4.3 mA
Quiescent current per BUCK converter (in addtion to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 5 V 15
Quiescent current per BUCK converter (in addtion to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 1 V 0.41
Quiescent current per BUCK converter (in addtion to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 5 V 0.46
IQ_TOTAL Quiescent current (Total) Typical Application: ACTIVE mode, all VIN pins combined, DMD, ILLUMINATION and PWR1,2 enabled, PWR3,4,5,6,7 disabled. 38 mA
INTERNAL SUPPLIES
VSUP_5P0V Internal supply, analog 5 V
VSUP_2P5V Internal supply, logic 2.5 V
DMD - LDO DMD
VDRST_VIN 6 12 20 V
VDRST_5P5V 5.5 V
PGOOD Power good DRST_5P5V Rising 80%
Faling 60%
OVP Overvoltage protection DRST_5P5V 7.2 V
Regulator dropout At 25 mA, VDRST_VIN= 5.5 V 56 mV
Regulator current limit(1) 300 340 400 mA
DMD - BUCK CONVERTERS
OUTPUT VOLTAGE
VPWR_1_VOUT Output Voltage 1.1 V
VPWR_2_VOUT Output Voltage 1.8 V
DC output voltage accuracy IOUT= 0 mA –3% 3%
MOSFET
RON,H High side switch resistance 25°C, VPWR_1,2_Boost – VPWR1,2_SWITCH = 5.5 V 150 mΩ
RON,L Low side switch resistance(1) 25°C 85 mΩ
LOAD CURRENT
Allowed Load Current. 3 A
IOCL Current limit(1) LOUT= 3.3 μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 5 V 120 ns
tOFF(MIN) Minimum off time(1) TA = 25°C, VFB = 0 V 270 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to High 72%
ILLUMINATION - LDO ILLUM
VILLUM_VIN 6 12 20 V
VILLUM_5P5V 5.5 V
PGOOD Power good ILLUM_5P5V Rising 80%
Falling 60%
OVP Overvoltage protection ILLUM_5P5V 7.2 V
Regulator dropout At 25 mA, VILLUM_VIN = 5.5 V 53 mV
Regulator current limit(1) 300 340 400 mA
ILLUMINATION - DRIVER A,B
VILLUM_A,B_IN Input supply voltage range 6 12 20 V
PWM
ƒSW Oscillator frequency 3 V < VIN < 20 V 600 kHz
tDEAD Output driver dead time HDRV off to LDRV on, TRDLY = 0 28 ns
HDRV off to LDRV on, TRDLY = 1 40
LDRV off to HDRV on, TRDLY = 0 35
OUTPUT DRIVERS
RHDHI High-side driver pull-up resistance VILLUM_A,B_BOOT – VILLUM_A,B_SW = 5 V, IHDRV = –100 mA 4.9 Ω
RHDLO High-side driver pull-down resistance VILLUM_A,B_BOOT – VILLUM_A,B_SW = 5 V, IHDRV = 100 mA 3 Ω
RLDHI Low-side driver pull-up resistance ILDRV = –100 mA 3.1 Ω
RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 2.4 Ω
tHRISE High-side driver rise time(1) CLOAD = 5 nF 23 ns
tHFALL High-side driver fall time(1) CLOAD = 5 nF 19 ns
tLRISE Low-side driver rise time(1) CLOAD = 5 nF 23 ns
tLFALL Low-side driver fall time(1) CLOAD = 5 nF 17 ns
OVERCURRENT PROTECTION
HSD OC High-Side Drive Over Current threshold External switches, VDS threshold(1). 185 mV
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.75 V
PGOOD
RatioUV Undervoltage protection 89%
INTERNAL RGB STROBE CONTROLLER SWITCHES
RON ON-resistance CH1,2,3_SWITCH 30 45 mΩ
ILEAK OFF-state leakage current VDS= 5.0 V 0.1 µA
IMAX Maximum current 6 A
DRIVERS EXTERNAL RGB STROBE CONTROLLER SWITCHES
CHx_GATE_CNTR_HIGH Gate control high level ILLUM_SW_ILIM_EN[2:0] = 7, register 0x02, ISINK= 400 µA 4.35 V
ILLUM_SW_ILIM_EN[2:0] = 0, register 0x02, ISINK= 400 µA 5.25
CHx_GATE_CNTR_LOW Gate control low level ILLUM_SW_ILIM_EN[2:0] = 7, register 0x02, ISINK= 400 µA 55 mV
ILLUM_SW_ILIM_EN[2:0] = 0, register 0x02, ISINK= 400 µA 55
LED CURRENT CONTROL
VLED_ANODE LED Anode voltage(1) Ratio with respect to VILLUM_A,B_VIN
(Duty cycle limitation).		 0.85x
8.6 V
ILED LED currents VILLUM_A,B_VIN ≥ 8 V. See register SWx_IDAC[9:0] for settings. 1 32 A
DC current offset, CH1,2,3_SWITCH RLIM = 4 mΩ –150 0 150 mA
Transient LED current limit range (programmable) 20% higher than ILED. Min-setting,
RLIM= 4 mΩ. 		11%
20% higher than ILED. Max-setting,
RLIM= 4 mΩ. Percentage of max current.		 133%
tRISE Current rise time ILED from 5% to 95%, ILED = 600 mA, transient current limit disabled(1). 50 µs
BUCK CONVERTERS - LDO_BUCKS
VPWR_VIN Input voltage range PWR1,2,5,6,7_VIN 16 19.5 20 V
VPWR_5P5V PWR_5P5V 5.5 V
PGOOD Power good PWR_5P5V Rising 80%
Falling 60%
OVP Overvoltage Protection PWR_5P5V 7.2 V
Regulator dropout At 25 mA, VPWR_VIN= 5.5 V 41 mV
Regulator current limit(1) 300 340 400 mA
BUCK CONVERTERS - GENERAL PURPOSE BUCK CONVERTERS(4)
OUTPUT VOLTAGE
VPWR_5,6,7_VOUT Output Voltage (General Purpose Buck1,2,3) 8-bit programmable 1 5 V
DC output voltage accuracy IOUT= 0 mA –3.5% 3.5%
MOSFET
RON,H High-side switch resistance 25°C, VPWR5,6,7_Boost – VPWR5,6,7_SWITCH = 5.5 V 150 mΩ
RON,L Low-side switch resistance(1) 25°C 85 mΩ
LOAD CURRENT
Allowed load current PWR6. 2 A
Allowed load current PWR5, PWR7. Buck converters should not be used. A
IOCL Current limit(1) LOUT= 3.3 μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 5 V 120 ns
tOFF(min) Minimum off time(1) TA = 25°C, VFB = 0 V 270 310 ns
START-UP
tSS Soft-start period 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to High 72%
AUXILIARY LDOs
VPWR3,4_VIN Input voltage range LDO1 (PWR4), LDO2 (PWR3) 3.3 12 20 V
PGOOD Power good PWR3_VOUT, PWR4_VOUT PWR3_VOUT and PWR4_VOUT rising 80%
PWR3_VOUT and PWR4_VOUT falling 60%
OVP Overvoltage Protection PWR3_VOUT, PWR4_VOUT 7 V
DC output voltage accuracy PWR3_VOUT, PWR4_VOUT IOUT= 0 mA –3% 3%
Regulator current limit(1) 300 340 400 mA
tON Turn-on time to 80% of VOUT = PWR3 and PWR4, C = 1 µF 40 µs
LDO2 (PWR3)
VPWR3_VOUT Output Voltage PWR3_VOUT 2.5 V
Load Current capability 200 mA
DC Load regulation PWR3_VOUT VOUT= 2.5 V, 5 ≤ IOUT ≤ 200 mA –70 mV/A
DC Line regulation PWR3_VOUT VOUT= 2.5 V, IOUT= 5 mA, 3.3 ≤ PWR3_VIN ≤ 20 V 30 µV/V
LDO1 (PWR4)
VPWR4_VOUT Output Voltage PWR4_VOUT 3.3 V
Load Current capability 200 mA
DC Load regulation PWR4_VOUT VOUT= 3.3 V, 5 ≤ IOUT ≤ 200 mA –70 mV/A
DC Line regulation PWR4_VOUT VOUT= 3.3 V, IOUT= 5 mA, 4 ≤ PWR4_VIN ≤ 20 V 30 µV/V
Regulator dropout IOUT = 25 mA, VOUT= 3.3 V, VPWR4_VIN= 3.3 V 48 mV
MEASUREMENT SYSTEM
AFE
G Amplifier gain (PGA) AFE_GAIN[1:0] = 01 1 V/V
AFE_GAIN[1:0] = 10 9.5
AFE_GAIN[1:0] = 11 18
VOFS Input referred offset voltage PGA, AFE_CAL_DIS = 1(1) –1 1 mV
Comparator(1) –1.5 +1.5
τRC Settling time To 1% of final value(1). 46 67 µs
To 0.1% of final value(1). 69 100
VACMPR_IN_1,2,3 Input voltage Range ACMPR_IN_1,2,3 0 1.5 V
LABB
τRC Settling time To 1% of final value(1). 4.6 6.6 µs
To 0.1% of final value(1). 7 10
VACMPR_IN_LABB Input voltage range ACMPR_IN_LABB 0 1.5 V
Sampling window ACMPR_IN_LABB Programmable per 7 µs 7 28 µs
COLOR WHEEL PWM
CLK_OUT Clock output frequency 2.25 MHz
VCW_SPEED_PWM_OUT Voltage range CW_SPEED_PWM_OUT Average value programmable in 16 bits 0 5 V
DIGITAL CONTROL - LOGIC LEVELS AND TIMING CHARACTERISTICS
VSPI SPI supply voltage range SPI_VIN 1.7 3.6 V
VOL Output low-level RESETZ, CMP_OUT, CLK_OUT. IO = 0.3 mA sink current 0 0.3 V
SPI_DOUT. IO = 5 mA sink current 0 0.3 × VSPI
INTZ. IO = 1.5 mA sink current 0 0.3 × VSPI
VOH Output high-level RESETZ, CMP_OUT, CLK_OUT. IO = 0.3 mA source current 1.3 2.5 V
SPI_DOUT. IO = 5 mA source current 0.7 × VSPI VSPI
VIL Input low-level PROJ_ON, LED_SEL0, LED_SEL1 0 0.4 V
SPI_CSZ, SPI_CLK, SPI_DIN 0 0.3 × VSPI
VIH Input high-level PROJ_ON, LED_SEL0, LED_SEL1 1.2 V
SPI_CSZ, SPI_CLK, SPI_DIN 0.7 × VSPI VSPI
IBIAS Input bias current VIO= 3.3 V, any digital input pin 0.1 µA
SPI_CLK SPI clock frequency(2) Normal SPI mode, DIG_SPI_FAST_SEL = 0, ƒOSC = 9 MHz 0 36 MHz
Fast SPI mode, DIG_SPI_FAST_SEL = 1, VSPI> 2.3 V, ƒOSC = 9 MHz 20 40
tDEGLITCH Deglitch time LED_SEL0, LED_SEL1(1). 300 ns
INTERNAL OSCILLATOR
ƒOSC Oscillator frequency 9 MHz
Frequency accuracy TA= 0 to 70°C –5% 5%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
(1) Not production tested.
(2) Maximum depends linearly on oscillator frequency fOSC.
(3) VIN must be higher than the UVLO voltage setting, including after accounting for AC noise on VIN, for the DLPA4000 device to fully operate. While 15.5 V is the min VIN voltage supported, TI recommends that the UVLO is never set below 16 V. 16 V gives margin above the minimum to protect against the case where someone suddenly removes VIN’s power supply which causes the VIN voltage to drop rapidly. Failure to keep VIN above 16.0 V before the mirrors are parked and VOFS, VRST, and VBIAS supplies are properly shut down can result in permanent damage to the DMD. Because 16 V is 500 mV above 15.5 V, when UVLO trips there is time for the DLPA4000 device and DLPC343x to park the DMD mirrors and do a fast shut down of supplies VOFS, VRST, and VBIAS. Regardless of the UVLO setting, , include enough bulk capacitance on VIN inside the projector to maintain VIN above 15.5 V for at least 100 µs after VIN power supply is suddenly removed causing a UVLO fault.
(4) General Purpose Buck2 (PWR6) currently supported, others may be available in the future.