JAJSFJ1 May 2018 DLPA4000
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fCLK | Serial clock frequency | 0 | 40 | MHz | |
tCLKL | Pulse width low, SPI_CLK, 50% level | 10 | ns | ||
tCLKH | Pulse width high, SPI_CLK, 50% level | 10 | ns | ||
tt | Transition time, 20% to 80% level, all signals | 0.2 | 4 | ns | |
tCSCR | SPI_SS_Z falling to SPI_CLK rising, 50% level | 8 | ns | ||
tCFCS | SPI_CLK falling to SPI_CSZ rising, 50% level | 1 | ns | ||
tCDS | SPI_MOSI data setup time, 50% level | 7 | ns | ||
tCDH | SPI_MOSI data hold time, 50% level | 6 | ns | ||
tiS | SPI_MISO data setup time, 50% level | 10 | ns | ||
tiH | SPI_MISO data hold time, 50% level | 0 | ns | ||
tCFDO | SPI_CLK falling to SPI_MISO data valid, 50% level | 13 | ns | ||
tCSZ | SPI_CSZ rising to SPI_MISO HiZ | 6 | ns |